Data transfer apparatus and data transfer system

ABSTRACT

A data transfer apparatus transfers serial data to and from a controller. The apparatus includes a first memory which stores at least one of command data and address data of the serial data transferred from the controller, and a second memory which stores a main body portion of the serial data to be transferred to and from the controller. Changeover circuitry is provided which selectively applies the serial data transferred from the controller to either the first memory or the second memory. Further, the changeover circuitry applies a clock signal received from the controller to one of the first memory or the second memory in accordance with a latch signal received from the controller. The second memory functions to selectively store the main data portion of the serial data received from the controller and to read the main data portion of the serial data transmitted to the controller.

FIELD OF THE INVENTION

The present invention relates to apparatus and system for digital datatransfer.

BACKGROUND OF THE INVENTION

A typical prior art system is shown in FIG. 1. An analog input signalsuch as sound signal is fed from a line 1 and is converted into adigital value in an analog/digital converter circuit 2, and is appliedto a processor 3 for data processing. The digital signal processed inthis processor 3 is sent to a digital/analog converter circuit 4 to beconverted into an analog signal, and is output from a line 5 to drive,for example, a speaker. A microcomputer 6 is connected to the processor3. The arithmetic processing speed of the processor 3 is faster thanthat of the microcomputer 6. To transfer the data from the microcomputer6 into the processor 3, the data from the microcomputer 6 is stored inseries in a receiving register 8 by way of a line 7.

In this way the data from the microcomputer 6 is transferred until thereceiving register 8 is filled up, when a flag Fl is set up on a line 9,and is applied to a control circuit 10. The content of the receivingregister 8 is stored in a memory 11. The control circuit 10 generates,when the flag Fl is set up, a signal for temporarily stoppingtransmission of the data from the microcomputer 6 through a line 14.After the content of the receiving register 8 is stored in the memory11, a signal indicative of this storing is given to the microcomputer 6from the control circuit 10, and the microcomputer 6 outputs theremaining data from the line 7 to the receiving register 8. Thus thecontent in the receiving register 8 is further stored in the memory 11as mentioned above.

The control circuit 10 repeats operations in every specified samplingperiod W shown in FIG. 2 (1). In this sampling period W, digital signalprocessing is conducted in period W1 shown in FIG. 2 (2), and in theremaining period W2 shown in FIG. 2 (3) the data from the microcomputer6 is stored in the memory 11 by way of receiving register 8.

In such a prior art system, if the period W1 for digital signalprocessing in the processor 3 is relatively long, the period W2 fortransferring the data from the microcomputer 6 to the processor 3becomes relatively short. Therefore, in order to transfer the data fromthe microcomputer 6 to the processor 3 securely, the sampling period Wmust be set sufficiently long. On the other hand, with each samplingperiod W, it is sometimes not necessary to transfer data from themicrocomputer 6 to the processor 3, and in such a case no processing ofthe processor 3 is carried out in the remaining period W3 (see FIG. 2(3)), and the time is thus wasted. In the prior art, since the data istransferred by program processing in this way, the period W1 for digitalsignal processing allowed in each sampling period W may become short, orit may be necessary to prolong the sampling period W, so that thequality of signal processing may deteriorate.

Likewise, when transferring data from the processor 3 to themicrocomputer 6, the content of the memory 11 is stored in thetransmitting register 12, and the content of this transmitting register12 is transferred to the microcomputer 6 by way of a line 13. If thereis much content to be transmitted, when the data is set in thetransmitting register 12, a signal indicative of this is given to thecontrol circuit 10 through a line 15, and a flag F2 is set up. Thecontrol circuit 10 outputs a signal to express the setting of thecontent in the transmitting register 12 to the microcomputer 6 through aline 14, so that the microcomputer 6 can accurately receive the contentof the transmitting register 12. In such data transfer from theprocessor 3 to the microcomputer 6, a same operation as in the operationdescribed in relation to FIG. 2 is effected, and the period W1 ofdigital signal processing that can be carried out in each samplingperiod W may be short, or it is necessary to elongate the samplingperiod W, which results in a deterioration of the quality of signalprocessing.

It is hence a primary object of the invention to present an apparatusand system for data transfer capable of increasing the time for digitalsignal processing, by transferring data between a controlling unit andprocessing unit mutually at high speed, eliminating wasted time, andcapable of simplifying the constitution while shortening the transfertime of data.

It is other object of the invention to present an apparatus and systemfor data transfer capable of reducing the data length for transfer whilesignificantly increasing the data transfer speed.

SUMMARY OF THE INVENTION

The invention relates to a data transfer apparatus for transferringserial data mutually with a control device, which comprises:

first memory means for storing at least one of command data and addressdata transferred from the control device,

second memory means for storing the data to be transferred to and fromthe control device, and

changeover means for changing over the data to be transferred from thecontrol device to either the first memory means or second memory means,

wherein the second memory means serves for both writing and reading forselectively storing the data to be transmitted to the control device aswell as the data received from the control device, and the changeovermean delivers by changing over the clock signal to be fed from thecontrol device to either first memory means or second memory means,depending on the latch signal received from the control device.

The invention moreover relates to a data transfer apparatus fortransferring serial data mutually between a control device and aprocessor, wherein

a signal line is disposed between the control device and the processor,and this signal line is intended to instruct either the reading actionstate of data or the writing action state to the processor or thecontrol device depending on the level of the signal delivered from thecontrol device or processor,

at least either one of the control device and processor being providedwith plural counting means for counting the above data or the number ofbits of its constituent components, and

reading/writing processing of the corresponding data or the constituentcomponents is effected by the output of end of counting of thecorresponding number of bits of the counting means, and data writing is,if effected, after data transfer, and then the intended address istransferred.

The invention moreover relates to a data transfer system fortransferring serial data mutually between a control device and aprocessor, wherein

a signal line is disposed between the control device and the processor,and this signal line is intended to instruct either the reading actionstate of data or the writing action state to the processor or thecontrol device depending on the level of the signal delivered from thecontrol device or processor, and

the intended address is transferred next to the data to be written whenwriting, and only the intended address is transferred when reading.

Conforming to the invention, the data may be mutually transferredbetween the control device and data processor. At this time, at leastone of the command data and address data to be transferred from thecontrol device is stored in the first memory means on the basis of theclock signal entered from the control device through the changeovermeans, depending on the latch signal. When the command data and addressdata of the data transferred from the control device is over, and as thesucceeding data is to be transferred, the changeover means is switchedto the second memory means, and the data is stored. In this way, writingprocessing of data is realized.

On the other hand, when reading out data from the data transfer deviceto the control device, at least one of the command data and the addressdata is transferred from the control device. When such data is stored inthe first memory means and the data transfer device reads out the heldcontent on the basis of the address data and stores into the secondmemory means, when the changeover means changes over the clock signalfrom the control device to the second memory means, so that the readingaction is realized in this way. Thereby, the apparatus for data transfercan increase the time for digital signal processing, by transferringdata between the controlling unit and processing unit mutually at a highspeed, eliminating wasted time and simplifying the constitution of thedata transfer apparatus.

The invention further relates to a system for transferring data mutuallybetween a control device and a processor, in which a signal line isdisposed between the control device and processor. Depending on thelevel of the signal delivered from the control device of processor onthis signal line, either the data reading action state or writing actionstate is instructed on the processor or control device.

Hence, for the reading action and writing action between the controldevice and processor, it is not necessary to send mutually correspondingcommands, and it is distinguished only by the level of the signal line.Further, by the data writing/reading, since only the minimum bit numberis transferred, the data length responsible for transfer may be reduced,and the data transfer is efficient, and the transfer speed issignificantly is increased. Moreover, whether in writing or in reading,since the address can be read out from the same position in the transferregister, a changeover circuit or the like is not needed, and theconstruction may be simplified.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram of a prior art system;

FIG. 2 (1)-(3) constitute a waveform diagram to explain the operation ofthe prior art system shown in FIG. 1;

FIG. 3 is a system diagram of a configuration according to a mainembodiment of the invention;

FIG. 4 is a block diagram showing an example of a basic configuration ofFIG. 3;

FIG. 5 is a block diagram showing a configuration of an embodiment ofthis invention;

FIGS. 6 (1)-(5) constitute a timing chart to explain the writing actionof the same configuration;

FIGS. 7 (1)-(6) constitute a timing chart to explain the reading actionof the same configuration;

FIG. 8 is a block diagram showing a configuration of an embodiment ofthe invention;

FIG. 9 is a block diagram showing an example of a decoder 35;

FIG. 10 is a block diagram showing an example of a decoder 36;

FIGS. 11 (1)-(5) constitute a timing chart to explain the operation ofthe same embodiment;

FIGS. 12 (1)-(2) show the relation between the data transfer sequenceand register;

FIG. 13 is a block diagram of an embodiment of the invention;

FIG. 14 (1)-(6) constitute a timing chart to explain the operation whenthe first plurality n and the second plurality m are equal to each otherin the embodiment shown in FIG. 13;

FIGS. 15 (1)-(8) constitute a timing chart to explain the operation whenthe first plurality n is less than the second plurality m;

FIGS. 16 (1)-(8) constitute a timing chart to explain the operation whenthe first plurality n exceeds the second plurality m;

FIG. 17 is a block diagram of a different embodiment of the invention;

FIG. 18 is a block diagram showing the composition of the receiving sideof an embodiment of the invention;

FIG. 19 is a block diagram showing the composition of the transmittingside of the same embodiment;

FIGS. 20 (1)-(6) constitute a timing chart to explain the operation ofthe same embodiment;

FIG. 21 is a block diagram of a sound signal processor 13 in anembodiment of the invention;

FIGS. 22 (1)-(9) and FIGS. 23 (1)-(2) are waveform diagrams to explainthe operation of the embodiment of the invention;

FIG. 24 and FIG. 25 are block diagrams showing a basic composition ofthe transmitting side and receiving side according to an embodiment ofthe invention;

FIGS. 26 (1)-(7) constitute a timing chart to explain the data transferby the configuration shown in FIG. 24 and FIG. 25;

FIG. 27 is a block diagram of an embodiment of the invention;

FIGS. 28 (1)-(8) constitute a waveform diagram to explain the operationof the embodiment shown in FIG. 27;

FIG. 29 is a block diagram showing a configuration of a sound signalprocessor 41 in an embodiment of the invention;

FIGS. 30 (1)-(5) constitute a waveform diagram to explain the operationof the embodiment shown in FIG. 29;

FIG. 31 is a drawing to explain the storing the transferring actions ofdata in processors 44, 48;

FIG. 32 is a block diagram showing the composition of processors DSP3,DSP4 for transferring data in an embodiment of the invention;

FIGS. 33 (1)-(4) constitute a waveform diagram to explain the datatransfer action between processors DSP3 and DSP4;

FIG. 34 is a block diagram to show the configuration when the datatransfer system of the invention is employed in the transfer of anacoustic signal;

FIG. 35 is a block diagram of an embodiment of the invention;

FIG. 36 is a block diagram showing the details of part of theconstitution of the embodiment shown in FIG. 35;

FIGS. 37(1)-(4) constitute a waveform diagram to explain the operationof data transfer in the constitution shown in FIG. 36;

FIG. 38 is a block diagram of a different embodiment of the invention;

FIG. 39 is a block diagram showing the configuration near processor DSP4in an embodiment of the invention;

FIG. 40 is a drawing to explain the operation when the function of anelectronic variable resistor is added to the processor DSP4;

FIG. 41 is a block diagram to show another embodiment of the invention;

FIG. 42 is a block diagram of an acoustic processor of the invention;

FIGS. 43 (1)-(7) constitute a waveform diagram to explain the operationof FIG. 42;

FIG. 44 is a block diagram of a processor;

FIG. 45 is a block diagram of an acoustic signal processor of theinvention;

FIGS. 46 (1)-(5) constitute a waveform diagram to explain the operationof FIG. 45;

FIG. 47 is a block diagram of a processor; and

FIG. 48 is a block diagram showing a configuration of a sound signalprocessor 21 in an embodiment of the invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT

FIG. 3 is a system diagram of a configuration according to a mainembodiment of the invention, and FIG. 4 is a block diagram showing anexample of the basic configuration of FIG. 3. Referring to thesedrawings together, the configuration of this embodiment is describedbelow. This configuration controls, for example, a car-mount acousticapparatus possessing several functions such as a radio receiver of FMwave band and AM wave band, cassette tape recorder, compact disc player,and digital audio magnetic tape player (DAT).

This embodiment processes signals of AM wave band receiver AM, FM waveband receiver FM, cassette tape recorder CS, compact disc player CD, anddigital audio magnetic tape player DAT. The outputs of receivers AM, FM,and cassette tape recorder CS are selected by a changeover switch SS1.This selected output is passed into a low pass filter LPF, in which highfrequency noise is removed, and is sent to an analog-to-digitalconverter (A/D converter) ADC to be digitized, and the digitized outputis applied to digital signal processors (hereinafter called processors)DSP1, DSP2.

Outputs of processors DSP1, DSP2 are fed into a digital-to-analogconverter (D/A converter) DAC to be converted into analog signals, whichare sent to the low pass filter LPF to be rid of high frequency noise,and are delivered from speakers SP as sound through an amplifier AMP. Onthe other hand, outputs from the compact disc player CD and digitalaudio tape player DAT are selected by changeover switches SS2, SS3, andthe selected output is fed into processors DSP1, DSP2. The processorsDSP1, DSP2 are controlled by a microcomputer CM, to which are connectedexternal memories EM1, EM2, such as static memories (S-RAM).

FIG. 4 shows the connection state of the microcomputer CM and processorDSP1. The processor DSP1 comprises a receiver RC and a sender SD. Thereceiver RC and sender SD possess mantissa registers RR1, RR2, RR3, RR4;SR1, SR2, SR3, SR4 for storing the mantissa sections of the floatingdecimal point type data to be received or sent, and also have indexregisters RI1, RI2, RI3, RI4; SI1, SI2, SI3, SI4 for storing the indexsections. In these registers (collectively mentioned by reference codesRR, SR; RI, SI), buffer registers Ra1 to Ra8; Rb1 to Rb8 (collectivelymentioned by reference codes Ra, Rb) are disposed correspondingly.

The buffer registers Ra, Rb are connected to a data bus DB, to which areconnected central processing unit CPU and memory M, by way of pluralgates G1, G2, respectively.

The processor DSP1 is equipped with a receiving register RX andreceiving-transmitting register RT to be used in data transfer with themicrocomputer, and the received data is stored in either register RX orRT by means of a changeover switch SS4. There is a cycle stillcontroller CC for controlling the operations of the registers RX, RT.The microcomputer CM is furnished with a transmitting register TX and areceiving register RX for transmitting and receiving data between theabove registers RX, RT, and there are buffer registers BT, BR forexchanging data between these registers RX, TX.

Embodiments

FIG. 5 is a block diagram showing a configuration of an embodiment ofthe invention. This embodiment contains an arithmetic control device 21realized by, for example an arithmetic processor, and a processor 22.The arithmetic control device 21 comprises a buffer register fortransmission 23 and a buffer register for reception 24, and these bufferregisters 23, 24 are connected to the address bus and data bus containedin the arithmetic control device 21 to access the data. Transmittingregister 25 and receiving register 26 are connected to these bufferregisters 23, 24.

The processor 22 comprises, for example, 4-bit command register 27 and12-bit address register 28, and to these registers 27, 28, transmissiondata D1 is fed from the transmitting register 25 of the arithmeticcontrol device 21. The content of the command register 27 is analyzed inthe command decoder 29, and a corresponding action is executed in theprocessor 22. On the other hand, the registers 27, 28 are read by acycle still control unit 30, and the address data is exchanged with theaddress bus 31 between timings of arithmetic processings.

The processor 22 also possesses a data register 32 of, for example, 24bits for storing the data main body to be transmitted which is containedin the transmission data D1. It is an important object of thisembodiment that this data register 32 can be used commonly fortransmission and reception for the arithmetic control device 21. Inthese registers 27, 28 and data register 32, the clock signal CKgenerated by the arithmetic control device 21 is entered as beingchanged over by the changeover switch 33 as described below.

The latch control signal LC as stated later to be delivered from thearithmetic control device 21 is entered in the data latch control unit34 which is provided in the processor 22, and the data latch controlunit 34 correspondingly controls the changeover mode of the changeoverswitch 33 and the data latch actions in the registers 27, 28, 32. Thecontent in the data register 32 is written into the memory 36 realizedby, for example, a random access memory, by the address data supplied inthe address bus 31 through the data bus 35, and this content is readout.

FIGS. 6(1)-(5) constitute a timing chart to explain the writing actionin the configuration shown in FIG. 5 . Referring to also FIG. 2, thewriting action of the embodiment is explained below. At time t1, thearithmetic control device 21 changes the chip select signal CS to a lowlevel as shown in FIG. 6 (1), and the processor 22 is selected. In turn,the processor 22 changes the transfer control signal TE to a low level,and the data transfer between the arithmetic control device 21 andprocessor 22 is realized. At this time, the data latch control unit 34is also reset, and the changeover switch 33 is changed over to the sideof registers 27, 28.

Afterwards, as shown in FIG. 6 (4), as the transmission data, thecommand data denoting the writing command and the address dataindicating the destination of writing of the data main body aretransferred to the command register 27 and the address register 28,according to the clock signal CK entered from the arithmetic controldevice 21. When transfer is started, the latch control signal LC is setto a low level as shown in FIG. 6 (3). Furthermore, at time t2 when thistransfer is complete, as shown in FIG. 6 (3), the latch control signalLC is set to high level. At this timing, the command data and addressdata are latched in the command register 27 and address register 28. Atthe same time, the changeover switch 33 is changed to the side of thedata register 32 by the data latch control unit. Next, in succession, asshown in FIG. 6 (2), the transfer control signal TE becomes a highlevel, and the transfer is prohibited.

At time t3, the transfer control signal TE becomes a low level so as tobe ready to transfer again, and the data main body to be stored in theaddress which is stored in the address register 28 is transferred to theprocessor 22 as shown in FIG. 6 (4). The arithmetic control device 21delivers a clock signal CK, and transfers the data main body to the dataregister 32. At the same time, the latch control signal LC is set to alow level. When this latch action is complete, the latch control signalLC is set to a high level, and the changeover switch 33 is changed againto the side of registers 27, 28.

Consequently the transfer control signal TE becomes a high level toprohibit transfer. Later, the chip select signal CS becomes a highlevel, and the writing action is complete.

FIGS. 7 (1)-(6) constitute a timing chart to explain the data readingprocessing from the processor 22 by the arithmetic control device 21 inthe configuration shown in FIG. 5. Referring to FIG. 3, the data readingprocessing is explained below. In the reading process, in thisconfiguration, first the chip select signal CS is set to a low level attime t5 as shown in FIG. 7 (1), and the processor 22 is selected. Thenthe transfer control signal TE becomes a low level, and the data can betransferred between the arithmetic control device 21 and the processor22. From the arithmetic control device 21, as shown in FIG. 7 (4), thecommand data denoting the reading command, and the address data tospecify the address in, for example, the memory 36 of the processor 22in which the data to be read is stored are transferred to the processor22. At the same time, the latch control signal LC is set to a low level.

At this time, similarly to the case of FIG. 6., the latch control signalis reset by the rise of the chip select signal CS, and the changeoverswitch 33 is changed to the side of registers 27, 28. Thus, the commanddata and address data which are transmission data D1 are written intothe command register 27 and address register 28. The contents of theseregisters 27, 28 are latched in the command register 27 and addressregister 28 at the timing where the latch control signal LC becomes ahigh level at time t6. At this time, the changeover switch 33 is changedto the side of register 32.

The latched address information is decoded next in the cycle stillcontrol unit 30, and the data of the corresponding address in, forexample, the memory 36 provided in the processor 22 is read out, and isstored in the data register 32. At time t7 after such storing, thetransfer control signal TE becomes low level. Afterwards, as shown inFIG. 7 (5), the data stored in the data register 32 is read outaccording to the clock signal CK from the arithmetic control device 21,and is stored as the reception data D2 of the arithmetic control device21.

When data transmission is complete in this way, as in the case of FIG.6, the latch control signal LC becomes a high level, and the transfercontrol signal TE and chip select signal CS sequentially become a highlevel, thereby finishing the reading processing.

In the above writing processing and reading processing, when the data tobe written after time t3 in FIG. 6 has, for example, 24 bits, the timerequired for this writing action is 753 μs, nearly the same as in theprior art, as calculated by the present inventor.

On the other hand, when reading data out of the processor 22, asexplained by reference to FIG. 3, the address of the data to be read outis transferred, and in this case, too, the necessary time has beenconfirmed to be nearly 753 μs, the same as in the prior art.

As stated above, the configuration shown in FIG. 5 can realize a sameaction as in the prior art. In this embodiment, the data register 32 isused for both reception and transmission, and the transfer relation hasbeen confirmed to be reduced by about 30% as compared with the prior artshown in FIG. 4. Incidentally the data length to be transferred may be,for example, 40 bits (5 bytes) in both reading and writing processings,the transfer time can be shortened by about 36% as compared with theprior art in the data reading action.

In the invention, the input destination of the data delivered from thecontrol device is changed over by changing the clock applied to thefirst and second memory means, because in the case where the datatransfer route itself to the first and second memory means is changedover, it is necessary to take in the data immediately when a specifiednumber of pieces of data is entered, and as a result the hardwareconfiguration becomes complicated and the time to take in the data isdefined, which are actually demerits.

In this embodiment, moreover, a synchronous communication to synchronizewith the external clock is shown, but this invention is also applicableto a synchronous communication (start/stop synchronous communication) byusing clock and others generated inside.

Thus, according to the invention, it is possible to transfer data athigh frequency by a simple construction.

FIG. 8 is a block diagram showing a configuration of an embodiment ofthe invention. This embodiment comprises an arithmetic control device 21realized, for example, by an arithmetic processing unit, and a processor22.

The arithmetic control device 21 is composed of a transmitting register23 and a receiving register 24, and the transmitting register 23delivers the write data DW into the processor 22, while the processor 22sends the read data DR into the receiving register 24.

The processor 22 incorporates the transfer register 27 composed of theaddress register 25 and data register 26 for storing the address anddata to make up the write data DW, and other data register 50 fordelivering internal data. The content of the transfer register 27 isstored in the address register 29 and data register 30 which make up thebuffer register 28. The contents of the address register 29 and dataregister 30 are exchanged with the address bus 31 and data bus 32 of theprocessor 22.

The processor 22 is provided with a gate control unit 33 for variouslogic gates (not shown). There is also a binary counter 34 for countingthe clock signals CK supplied from the arithmetic control device 21. Theoutput of the binary counter 34 is applied in parallel to the decoders35, 36. The outputs of the decoders 35, 36 are fed into one of the inputterminals of two-input AND circuit 37, 38, respectively.

To the AND circuit 38, a control signal R/W for indicating either thereading action state or writing action state to the processor 22 isentered, depending on whether the level is high or low, from thearithmetic control device 21 through the line 39 as stated later. At theother input terminal of the AND circuit 37, a signal being inverted fromthe control signal R/W in the inverter circuit 40 is fed. The outputs ofthe AND circuits 37, 38 are entered in the OR circuit 41, and the outputof the OR circuit 41 is applied to the address register 29 and dataregister 30 as latch control signal.

FIG. 9 and FIG. 10 are block diagrams showing the configuration of thedecoders 35, 36. In this embodiment, of the data transferred between thearithmetic control device 21 and the processor 22, the address data has16 bits and the main body data has 24 bits, and therefore, the datalength of 40 bits is assumed in the following explanation. The decoder35 uses the output of the lower 6 bits (b5, b4,b3,b2,b1,b0) of thebinary counter 34, for example as shown in FIG. 9. This output of thelower 6 bits is entered in the AND circuit 43 through signal lines 42 to47 from the lower bit side. On the signal lines 42, 43, 44, 46, thereare respective inverter circuits 49 to 52. The output of the AND circuit48 becomes a high level when the lower 6 bits of the binary counter 34are

    (b5,b4,b3,b2,b1,b0)=(1,0,1,0,0,0)                          (1)

and this case corresponds to 40 in decimal notation.

The decoder 36 basically has the same constitution, and the lower 5 bitsof the binary counter 34 are used. From the lower bit side, the contentof each bit is entered in the AND circuit 58 through signal lines 53 to57. At this time, inverter circuits 59 to 62 are disposed on the signallines 53 to 56. By the output of such decoder 36, the output of the ANDcircuit 58 becomes a high level when the lower 5 bits are

    (b4,b3,b2,b1,b0)=(1,0,0,0,0)                               (2)

and this case corresponds to 16 in decimal notation.

FIGS. 11 (1)-(5) constitute a timing chart to explain the operation ofthis embodiment. Referring now to these drawings together, the operationof this embodiment is described below. The symbols (1), (2) . . . (14)which follow correspond to the processing steps denoted by the circledreference numerals shown in FIG. 11. In the reading cycle time SRstarted from t11, (1) first the control signal R/W is set to high level,and it is instructed to read out the data from the processor 22. (2)Next, as shown in FIG. 11 (1), the chip select signal CS is set to a lowlevel, and the processor 22 is selected.

(3) The arithmetic control device 21, as shown in FIG. 11 (4), starts totransfer the address in which the data to be read in the processor 22 isstored, to the processor 22. Here (4) the processor 22 set the transferpermit signal TE to high level as shown in FIG. 11 (3), and the transferfrom the processor 22 is prohibited. When transfer of the address data63 is complete, the processor 22 reads out the internal data of theaddress, and when the output to the arithmetic control device 21 iscomplete, (5) at time t12, the transfer permit signal TE is set to a lowlevel, and the transfer prohibit state is canceled.

(6) On the basis of the clock signal CK from the arithmetic controldevice 21, as shown in FIG. 11 (5), the data is read out from theprocessor 22 into the arithmetic control device 21. When the datatransfer is over, (7) at time t13, the transfer permit signal TE is set(8) to a low level, and the transfer prohibit state is canceled again.This ends the data reading processing.

In the writing cycle SW, (9) the control signal R/W is set to a lowlevel, and the writing action from the arithmetic control device 21 tothe processor 22 is indicated.

(10) Next, as shown in FIG. 11 (4), the arithmetic control device 21sends out (11) the address data 65 in succession to the main body data64 to be stored in the processor 22. (12) When send-out of the addressdata 65 is started, the transfer permit signal TE becomes high level atthe processor 22 side, and the transfer is prohibited. (13) When thetransfer of the address data 65 is complete and writing into thespecified address of the internal memory is complete, the transferpermit signal TE becomes a low level, and the transfer is ready.

(14) Sequentially, at the arithmetic control device 21 side, the chipselect signal CS is set to a high level, and data writing is finished.

At this time, as shown in FIG. 8, while the control signal R/W is a highlevel, the AND circuit 38 is selected. In order words, in order totransfer data, the clock signals delivered from the arithmetic controldevice 21 are counted by the binary counter 34, and its output isdelivered to the decoders 35, 36 as explained by reference to FIG. 9 andFIG. 10 . During the period of reading cycle SR, the decoder 36 isselected by the AND circuit 38, and when the binary counter 34 counts 16bits as explained in relation to FIG. 10 , the output of the AND circuit58 is changed to the high level, and the data is latched into the bufferregister 28.

FIGS. 12 (1)-(2) show the setting state of the address and data in theregister, in which FIG. 12 (1) indicates the data reading mode, and FIG.12 (2) denotes the data writing mode.

In this way, when transferring the address from the address register 25to the buffer register 29, it is sufficient to read out always from thesame position, and changeover circuit or the like is not necessary.

At this time, when there are only 16 bits as mentioned above, theaddress data 63 is only transferred, and the address data stored in theaddress register 25 is latched in the address register 29 of the bufferregister 28. By thus latched address data, reading of internal memoryafter time t12 is effected.

In the writing cycle SW, on the other hand, the control signal R/W is ata low level, and the decoder 35 is selected by the AND circuit 37. Atthis time, when counting of 40 bits is finished by the binary counter34, a latch control signal is delivered to the buffer register 28. Sucha case corresponds to transfer of main body data 64 and address data 65after time t3 in FIG. 11, and when transfer of such address data 65 iscomplete, the latching action from the transfer register 27 to thebuffer register 28 is effected.

By this embodiment, as is obvious from the description herein, thecommand 15 explained in the prior art may be deleted from the transferdata, and the dummy main body data 17 may be also eliminated. Hence, thedata length necessary for transfer is significantly shortened, and thetransfer speed is increased, while the transfer efficiency is notablyenhanced.

The composition of the decoders 35, 36 is, however, not limited to theconfigurations in FIG. 9 and FIG. 10.

Thus, according to this invention, reading action and writing actioncarried out between the control device and the processor may bedistinguished only by the level of the signal line, without having tosend the corresponding commands to each other. Further, when taking outthe address from the transfer register to the buffer register, it issufficient to read out only from the same position, and any hardware forchangeover is not needed, and the construction may be simplified.Furthermore, the data length responsible for transfer may be reduced,and the data may be transferred efficiently, while the transfer speedmay be superbly increased.

FIG. 13 is a block diagram of an embodiment of the invention. The datais sequentially transferred in series bits, from a processor A toanother processor B. The processor A is provided with transmitting means8, and the other processor B has receiving means 9. The data to betransmitted at the transmitting means 8 are stored in first transmittingregisters A1 to An in a total number of n, and the store cell of eachbit is indicated by reference code a11, a12, a13 . . . ; a21, a22, a23,. . . ; to an1, an2, an3, . . . The data of every bit from thesetransmitting registers A1 to An are sequentially transferred to thereceiving means 9 from the line l1 through OR gate G1. In thesetransmitting registers A1 to An, signals for synchronizing are givenfrom the first n cells CA1 to CAn of the shift register CA.

From the clock signal generator circuit 10 to line MCLK, a clock signalof a predetermined specified period is provided. This clock signalgenerator circuit 10 leads out one clock signal once in every n times ofthe clock signal MCLK to the line CK1, and applies it to the shiftregister CA. The shift register CA, responding to the clock signal byway of line CK1, sets the first cell CA1 to logic 1, and the remainingstore cells CA2 to CAn to logic 0. Further, responding to the clocksignal by way of the line MCLK, the shift register CA sequentially movesthe single store cells CA1 to CAn of which logic is 1. This shiftregister CA does not return the initial cell CA1 to logic 1, if morethan n clock signals are entered from the line MCLK, as far as clocksignal is not entered through line CK1, and in the period while theclock signals through the line MCLK are being fed by the numberexceeding the plurality n as mentioned above, a11 cells CA1 to CAnremain at logic 0 unless the clock signals are fed from the line CK1. Inthe explanation to follow, the reference codes MCLK, CK1 denote thelines, and may also indicate the clock signals by way of such lines.

At the receiving means 9, second m receiving registers B1 to Bm areprovided, and data are commonly applied to these receiving registers B1to Bm by way of line l1. This shift register CB possesses a structuresimilar to that of the above shift register CA, and also has cells CB1to CBm. When the logic 1 signals from these cells CB1 to CBm arerespectively applied to the corresponding receiving registers B1 to Bm,the store contents of the cells b11, b12, b13, . . . ; b21, b22, b23, .. . ; b31, b32, b33, . . . ; ˜; bm1, bm2, bm3, . . . are led into thereceiving registers B1 to Bm bit by bit. In the shift register CB, clocksignals MCLK, CK1 from the clock signal generator circuit 10 arerespectively applied.

Referring now to FIGS. 14 (1)-(6), the operation when the first pluralnumber n and second plural number m are equal to each other (n=m) isexplained below. FIG. 14 (1) shows the sequential data of the bits whichare led out into the line l1 through the OR gate G1 from transmittingregisters A1 to An of the processor A. Such data is led out insynchronism with the clock signal MCLK shown in FIG. 14 (2). The clocksignal CK1, as shown in FIG. 14 (3), is generated at every plural n (=m)clock signals MCLK. To the cells CA1, CA2, CA3 of the shift register CAto the transmitting registers A1, A2, A3, transmission signals T1a, T2a,T3a are sequentially led out as shown in FIG. 14 (4), (5), and (6), andthese signals T1a, T2a, T3a correspond to the fact that the contents ofthe cells CA1, CA2, CA3 are logic 1, and a similar operation isconducted thereafter. Thus, over a whole cycle W, the contents of thefirst cells a11, a21, a31, . . . , an1 of the transmitting registers A1to An are sent out. In the subsequent cycles, the data from the secondcells a12, a22, a32, . . . , an2 of the transmitting registers A1 to Anare sequentially led out. Repeating such operation, the contents of thetransmitting registers A1 to An are led out into line l1, andtransferred.

At the processor B, in the receiving means 9, reception to the cells ofthe receiving registers B1 to Bm is effected on the basis of the outputfrom one cell of which logic is 1 out of the cells CB1 to CBm of theshift register CB. In other words, the transmitting register A1corresponds to the reception register B1, and the content of the cella11 is transferred to the cell b11 and stored, while the content of thecell a21 of the transmitting register A2 is transferred to the cell b21of the receiving register B2 to be stored. Thereafter, similarly, thecontent of the cell an1 of the transmitting register An is stored in thecell bm1 of the receiving register Bm. In this way, data transfer of onecycle is complete.

Here, a clock signal CK1 is generated, and the first transmittingregister A1 and receiving register B1 of the next cycle correspond toeach other, and thereafter the contents of the cells a12, a22, . . . ,an2 of the transmitting registers A1, A2, . . . , An are sequentiallystored in the cells b12, b22, . . . , bm2 of the receiving registers B1,B2, . . . , Bm.

FIGS. 15 (1)-(8) constitute a timing chart to explain the operation whenthe first plural number n is less than the second plural number (n<m).As shown in FIG. 15 (1), from the transmitting registers A1 to An toline l1, the data of cells a11, a21, . . . , an1 of each stage aresequentially sent out. In the period while the clock signals MCLK shownin FIG. 15 (3) are being generated over the plural number n, data is notsent out on line l1. At the receiving means 9, reception of data to thefirst stage cells b11 to bml of the receiving registers B1 to Bm ofsecond plural number m is realized as shown in FIG. 15 (2), in responseto the clock signal MCLK.

Every time a clock signal MCLK of a plural number m is generated, oneclock signal CK1 is generated, which causes to transfer the data of thenext cycle. The waveform of clock signal CK1 is as shown in FIG. 15 (4).Of the signals being led out from cells CB1 to CBm of the shift registerCB, those representatively indicated by reference codes T1b, T2b, T3b, .. . , Tmb are respectively shown in FIG. 15 (5), (6), (7) and (8).

FIG. 16 is a drawing to explain the operation when the first pluralnumber n exceeds the second plural number (n>m). From the transmittingmeans 8, the bit-sequential data as shown in FIG. 16 (1) is transferredto line l1. At the receiving means 9, the data can be stored to thefirst stage cells b11, 2b1, . . . , bm1 of the receiving registers B1 toBm as shown in FIG. 16 (2), and if a clock signal MCLK shown in FIG. 16(3) is further applied later, storing in the receiving registers B1 toBm in that cycle will not be enabled. The clock signal CLK is generatedupon every generation of clock signal MCLK of very first plural number nas shown in FIG. 16 (4). In this way, the signal of logic 1 issequentially led out into cells CA1 to CAn of the shift register CA ofthe transmitting means 8 as shown in FIG. 16 (5), (6), (7) and (8), andthe data transfer from the first stage cells a11, to an1 of thetransmitting registers A1 to An of the first plural number n isfinished. In the second cycle, the data is transferred from the secondcells a12 to an2 of the transmitting registers A1 to An, and is receivedat the receiving means 9.

In a further different embodiment of the invention, it may be alsopossible to compose so that one clock signal CK1 may be generated everytime pulses of clock signal MCLK are generated by a predetermined numberexceeding the first plural number h and second plural number m.

FIG. 17 is a block diagram of a still different embodiment of theinvention, in which between the transmitting means 81 and receivingmeans 91, digital sound signals in a total of two channels of 16 bitseach are transferred, and from another transmitting means 82 toreceiving means 92, sound signals in a total of four channels of 16 bitseach are transferred. Of the four cells of shift register CAa, the firsttwo cells are given to transmitting registers A1a, A2a individuallypossessing 16 cells corresponding to each one of two channels, and theiroutputs are respectively applied to the receiving registers B1a, B2afrom the OR gate G2 through line l2. To these receiving registers B1a,B2a are applied signals from the first two cells of the shift registerCBa having four cells.

The outputs from each cell of shift register CAb at the transmittingmeans 82 possessing cells corresponding to four channels are given tothe transmitting registers A1b to A4b corresponding to each channel. Thetransmitting registers A1b to A4b possess 16-bit cells, and theiroutputs are applied to the receiving registers B1b to B4b of thereceiving means 92 by way of line l3 from the OR gate G3. To thesereceiving registers B1b to B4b are applied signals from the shiftregister CBb having four cells. Thus, between the transmitting andreceiving means 81, 91, the 2-channel portion of sound signals istransferred, while between the transmitting and receiving means 82, 92,the sound signals of 4-channel portion are transferred, and the datatransfer periods are identical.

The invention may be embodied in a wide range for data transfer.

In the above embodiment, the data is sent out bit by bit from eachtransmitting register to receiving register, but in another embodimentof the invention it may be also possible to design to transfer pluralbits of each transmitting and receiving register in batch.

Thus, according to the invention, it is possible to transfer variousdata which are different, for example, in the number of pieces ofinformation, smoothly and in a simple construction.

FIG. 18 is a block diagram showing the composition of the receiving sideof an embodiment of the invention, and FIG. 19 is a block diagramshowing the composition of its transmitting side. Referring now to FIGS.18 and 19, the composition of this embodiment is described below. Thereceiving side shown in FIG. 18 of this embodiment comprises a transferregister 45 composed of four shift registers, for example, 41, 42, 43,44. This transfer register 45 is composed to possess functions of bothtransfer registers 1, 21 and buffer registers 2, 22 as explained inrelation to the prior art later.

Between shift registers 41 and 42, and 43 and 44, changeover switches46, 47 are disposed, and they are connected to another changeover switch49 provided in the receiving line 48 for receiving the transfer data. Adata bus 50 is connected to the transfer register 45.

The structure of the transmitting side in FIG. 19 is similar to thereceiving side shown in FIG. 18, comprising, for example, a transferregister 55 composed of four shift registers 51, 52, 53, 54, changeoverswitches 56, 57 disposed between the shift register 51 and 52, and 53and 54, and a changeover switch 59 connected between these changeoverswitches 56, 57 and the transmission line 58.

The changeover switches 46, 47 are controlled by a clock signal CK3which is described later, and the shift action of the shift registers 41to 44 is executed by the internal clock signal CK3 generated internally.The switching action of the changeover switch 49 is realized by asynchronous signal SY1 which is described later.

The changeover switches 56, 57 are controlled by the clock signal CK3supplied to the shift registers 51 to 54, and the changeover switch 59is controlled by the synchronous signal SY1 mentioned later.

FIGS. 20 (1)-(6) constitute a timing chart for explaining the operationof this embodiment. Referring also to FIG. 18, the operation of thisembodiment is described below. First, the receiving action of thisembodiment is described. When the transfer data to be received reachesthe reception line 48, the changeover switch 49 is alternately changedto the changeover switches 46, 47 in every half period relating to theperiod W1 of the synchronous signal SY1 as shown in FIG. 20 (1). Whilethe changeover switch 49 is selected at the switch 46 side, thechangeover switch 46 changes over at the rise timing and fall timing ofthe clock signal CK3 shown in FIG. 20 (4), and the transfer data on thereception line 48 is stored in the shift registers 41, 42, bit by bit atthe rise of the clock signal CK4 generated internally.

In this way, in half period of synchronous signal SY1, data 1, 2 aretransferred to the shift registers 41, 42 as shown in FIG. 20 (2) and(3), and at time t3 in FIG. 20 (1) the changeover switch 49 is selectedto the switch 47 side, and data 3, 4 are written into the shiftregisters 43, 44 in the same manner.

This time, the transfer register 45 is connected to the data bus 50, andtherefore in the first half period W1a in FIG. 20 (1) while data istransferred to the shift registers 41, 42, if there is data alreadystored in the shift registers 43, 44, the operator can freely access tothe data through the data bus 50. In the second half period W1b in FIG.20 (1), the same operation is done on the shift registers 41, 42. Thatis, in the receiving action of the embodiment, different registers areused for data access parallel to the receiving action.

The transmitting action is next described referring to FIG. 19. In thiscase, too, the operation is basically same as the receiving action. Thedata 1 to 4 to be transmitted are stored in the shift registers 51 to 54through data bus 50, and at time t4 in FIG. 20 the changeover switch 59is, for example, to the changeover switch 57 side, when the changeoverswitch 57 is alternately changed to the shift registers 53, 54 by theclock signal CK3, so that the contents in the shift registers 53, 54 areread out bit by bit at every rise and fall of CLK4 similarly. At time t3in FIG. 20, when this reading action is finished, the changeover switch59 is changed to the switch 56 side, and by the operation of thechangeover switch 56 same as that of the changeover switch 57, thememory contents in the shift registers 51, 52 are led out into thetransmission line 58.

While the contents in the shift registers 53, 54 are being transmitted,the contents in the shift registers 51, 52 where data 1, 2 are storedcan be freely accessed through the data bus 50. While the contents inthe shift registers 51, 52 are being transmitted, of course, the sameprocessing is carried out on the memory contents of the shift registers53, 54.

In this embodiment, thus, parallel to the transmission/reception actionof transfer data, during the period of transmission/reception of thedata to be transferred, the remaining data may be freely read out orwritten in. As a result, the composition of, for example, the processor,is notably simplified.

In this way, according to the invention, when transferring data, it isnot necessary to prepare the shift register group for temporarilystoring the data to be transferred in the same number as the shiftregister group responsible for transfer, and the construction may benotably simplified.

FIG. 21 is a block diagram of a processor in an embodiment, in which asound signal processor 13 is used as an example. The analog soundsignals of right and left channels to be fed in input terminal T areconverted into digital sound of two channels in an analog/digitalconverter circuit 14, and are applied to a processor DSP1 through line15. At this processor DSP1, for example, tone control is executed. Theoutput of the processor DSP1 is applied to a processor DSP2 through line16.

At this processor DSP2, the sound signals in two channels applied fromthe line 16 are further processed digitally, and in order to enhance thepresence as in the sound system, sound signals in four channels areproduced in order to deliver them to speakers disposed at the front leftside FL, front right side FR, rear left side Rl, and rear right side RR,and the sound signals of 16 bits each of the front left and right sidesFL, FR are stored in series in the shift register 17, while the soundsignals of the rear left and right side RL, RR are stored in the othershift register 18. In the shift registers 17, 18, the speakerconfiguration and the corresponding digital sound signals arerepresented by the same reference codes FL, FR; RL, RR.

From the clock signal generator 19, a first clock signal CLK1 having apredetermined specific frequency shown in FIG. 22 (1) is led out intothe line 20, and is given as an external clock signal to the inputterminal 21 of the processor DSP2. This external clock signal CLK1 isapplied to the frequency converter circuit 22 disposed in the processorDSP2. This frequency converter circuit 22 is, for example, composed of amonostable multivibrator, and applies a clock signal having a frequencytwice that of the external clock signal CLK1 as shown in FIG. 22 (2)into the clock selection circuit 33 through the line 23, in response tothe rise and fall of the external clock signal CLK1 applied to the inputterminal 21. The external clock signal CLK1 applied to the inputterminal 21 is also applied to the clock selection circuit 33 directlythrough line 24. A clock signal generator circuit 34 is composed of thefrequency converter circuit 22 and clock selection circuit 33.

The clock selection circuit 33 changes over and leads out the clocksignal through line 23 and external clock signal CLK1 through line 24,in response to the voltage level of the control terminal 35. At thecontrol terminal 35, an output from the control input circuit 36 isapplied, and this control input circuit 36 is composed of resistance 37and switch 38, and one of the terminals of the resistance 37 isconnected to the high level power source, while the other terminal isconnected to one of the contacts of the switch 38. The other contact ofthe switch 38 is grounded. In this way, the potential at the connectionpoint of the resistance 37 and switch 38 is applied to the clockselection circuit 33 through control terminal 35.

Therefore, when a control signal as shown in FIG. 22 (3) is entered fromthe control terminal 35, the clock selection circuit 33 applied theclock signal shown in FIG. 22 (4) to the changeover control circuit 25.The changeover control circuit 25, corresponding to the input clocksignal, leads out the changeover circuits of mutually reverse polaritiesas shown in FIG. 22 (5), (6) to the line 26 and line 27.

The changeover signal coming out to the line 26 is also applied to theshift register 17 and to the AND gate G1. The changeover signal comingout to the line 27 is applied to the shift register 18 and the other ANDgate G2. The shift register 17, responding to the changeover signal fromthe line 26, sequentially leads out bit by bit the sound signals of 16bits each of the front left and right side FL, FR being stored there asshown in FIG. 22 (7).

Likewise, the shift register 18, responding to the changeover signalfrom the line 27, sequentially leads out bit by bit the sound signals of16 bits each of the rear left and right side RL, RR as shown in FIG. 22(8). FL1 to FL4 in FIG. 22 (7) represent the data of the first to fourthbit of the sound signal of the front left side FL, and similarly RL1 toRL3 in FIG. 22 (8) denote the data of the first to the third bit of thesound signal of the rear left side RL.

The sound signals of each bit from the shift registers 17, 18 arerespectively applied to the AND gates G1, G2. The sound signals from theAND gates G1, G2 are respectively applied to two digital/analogconverter circuits 30, 31 through the output terminal 28 and line 29from the OR gate G3. The digital signal led out from the output terminal28 is as shown in FIG. 22 (9). In this way, responding to the externalclock signal CLK1 applied to the input terminal 21, the sound signalstored in the shift registers 17, 18 is sequentially led out in seriesalternately bit by bit from the output terminal 28.

The clock signal from the clock signal generating circuit 19 is directlyapplied to the digital/analog converter circuit 30 from the line 20, andis also applied to the other digital/analog converter circuit 31 throughthe inverter circuit N1. The digital/analog converter circuits 30, 31are identical in structure. The digital/analog converter circuit 30responds to the rise of the external clock signal CLK1 shown in FIG. 22(1) through the line 20, and receives and stores the sound signalthrough the line 29 bit by bit.

Therefore, the digital/analog converter circuit 30 receives only thesound signal stored in the shift register 17 indicated by referencecodes FL1, FL2, FL3, and so forth, out of the digital sound signals onthe line 29 shown in FIG. 22 (9), sequentially bit by bit, and convertsit into analog sound signal in a total of two channels of the front leftand right side FL, FR, and leads out.

The other digital/analog converter circuit 31, responding to the rise ofthe clock signal through the inverter circuit N1, receives only thesound signal stored in the shift register 18 indicated by referencecodes RL, RL2, RL9, and so forth, out of the sound signals shown in FIG.22 (9), sequentially bit by bit, and converts into analog sound signalin a total of two channels of the rear left and right side RL, RR, andleads out. For the sake of simplicity of explanation, here, an exampleof using clocks of a same frequency is demonstrated, but usually whenthe control input is of low level, multiple data can be transferred byclock input at faster speed.

In this way, while a clock signal from the frequency converter circuit22 is applied to the changeover control circuit 25, the shift registers17, 18 can transfer the data into the digital/analog converter circuits30, 31 at a frequency twice that of the external clock signal CLK1 fromthe clock signal generator circuit 19, and the sound signals for theportion of 4 channels can be transferred to using a same external clocksignal CLK1 as the two-channel sound signal through the lines 15, 16.

In a special state of use such as when debugging, a high-speed secondexternal clock signal CLK2 is issued from the clock signal generatorcircuit 19 as shown in FIG. 23 (1). At this time, the clock signal fromthe frequency converter circuit 22 cannot follow up such rapid externalclock signal CLK2 by the effect of the circuit constant element or thelike, and therefore by operating the switch 38 to lead out this externalclock signal CLK2 through the line 24 from the clock selection circuit33, the data can be transferred securely as shown in FIG. 23 (2) withoutcausing transfer error or other trouble.

Thus, in this sound signal processor 13, external clock signals CLK1,CLK2 from the clock signal generator circuit 19 through the line 24, andthe clock signal having a frequency twice that of the external clocksignal CLK1 from the frequency converter circuit 22 through the line 23are changed over by the clock selection circuit 33, and are used as aninternal clock signal in the processor DSP2, and therefore the data canbe transferred at a frequency twice that of the external clock signalCLK1, and moreover in a special state of use such as when debugging,data can be transferred in correspondence to the high speed externalclock signal CLK2.

The invention may be embodied not only for processing of sound signals,but also widely in other technical fields. Instead of the digital/analogconverter circuits 30, 31, circuits having constructions for otherdigital signal processings may be employed.

According to the invention, as is clear herein, the output data from thefirst processor may be alternately transferred to two second processorsin a simple structure. Further, since it is designed to lead out bychanging over the external clock signal and the clock signal from thefrequency converter means by the use of the clock selection means, theprocessing circuit can, for example, process arithmetically or transferdata at a speed of desired times the external clock while responding tothe external clock signal, on the basis of the clock signal generated bythe frequency converter means, and can also process according to theclock signal when the frequency of the external clock signal is changed.

FIG. 24 is a block diagram showing the composition of the transmissionside according to an embodiment of the invention, and FIG. 25 is a blockdiagram showing the composition of the reception side of the same. Inthis embodiment, the group data composed of two-word data istransferred, and the one-word data contains, for example, 32 bits. Inthe composition of the transmission side shown in FIG. 24, there iscontained, for example, a transfer register 44 composed of shiftregisters 41, 42, 43 possessing a capacity of 32 bits each. Thistransfer register 44 is composed so as to contain the functions of bothbuffer register 22 and transfer register 21 as explained in relation tothe background technology as mentioned later.

To the transfer register 44, a parallel signal is entered from the databus 47 through changeover switches 45, 46 which are the second switchingmeans. The shift registers 41 to 43 contained in the transfer register44 are connected to the transmission line 49 for transmitting serialsignals through the changeover switch 48 which is the first switchingmeans.

The changeover switch 48 has input terminals 48a, 48b, 48c, and theshift registers 41, 42, 43 are respectively connected to these inputterminals. Switching of the changeover switch 48 is based on thesynchronous signal SY1 which is mentioned later, and serial signalsdelivered by the shift registers 41 to 43 are selectively led out to thetransmission line 49 as a result of this switching.

The changeover switches 45, 46 respectively possess output terminals45a, 45b, 45c; 46a, 46b, 46c. The output terminals 45a, 46a areconnected to the shift register 41, and the output terminals 45b, 46bare connected to the shift register 42, and the output terminals 45c,46c are connected to the shift register 43. Changeover switches 45, 46changeover as shown below on the basis of the synchronous signal SY1, sothat the parallel inputs from the data bus 47 may be selectively fedinto the shift registers 41 to 43.

Referring next to FIG. 25, the structure of the receiving side isexplained below. The composition of the receiving side shown in FIG. 25is similar to that of the transmission side shown in FIG. 24, and itcontains a transfer register 53 composed of shift registers 57, 58, 59.To the shift registers 57 to 59, serial signals are selectively enteredfrom the reception line 54 for receiving serial data through thechangeover switch 51 which is the first switching means. The shiftregisters 57 to 59 are connected to the data bus 60 through changeoverswitches 55, 56 which are second switching means.

The changeover switch 51 possesses output terminals 51a, 51b, 51c, andthese output terminals are respectively connected to the shift registers57, 58, 59. The switching action of the changeover switch 51 is based onthe synchronous signal SY1, and as a result the serial data through thereception line 54 is selectively entered into the shift registers 57 to59.

The changeover switches 55, 56 possess input terminals 55a, 55b, 55c;56a, 56b, 56c. The input terminals 55a, 56a are connected to the shiftregister 57, and the input terminals 55b, 56b are connected to the shiftregister 58, and input terminals 55c, 56c are connected to the shiftregister 59. The switching action of the changeover switches 55, 56 isbased on the synchronous signal SY1, and as a result the parallel datais selectively applied to the data bus 60 from the shift registers 57 to59.

Clock signals CK1 are applied to the shift registers 41, 42, 43 in thecomposition of the above transmission side and shift registers 57, 58,59 in the composition of the reception side, which realizes the shiftaction.

FIGS. 26 (1)-(7) constitute a timing chart for explaining the datatransfer action in the above composition. FIG. 26 (1) shows thesynchronous signal SY1, and FIG. 26 (2) indicates the data to be appliedto the data bus 60 in each period, and FIG. 26 (3) to (5) respectivelyrepresent the state of changeover switches 45 (55), 45 (56), and 48(51). Furthermore, FIG. 26 (6) indicates the clock signal CK1 and FIG.26 (7) shows the data to be led out into the transmission line 49(reception line 54). In FIG. 26 (1), reading of data into the transferregister 44 is indicated by the upward arrow. In FIG. 26 (3) to (5),input (output) terminals selected by the individual changeover switchesare shown, and the input (output) terminals connected to the shiftregisters 41, 57 are represented by reference code a, the input (output)terminals connected to the shift registers 42, 58 by reference code b,and the input (output) terminals connected to the shift registers 43, 59by reference code c.

Now, referring to FIGS. 24 and 26 , the operation at the transmissionside is explained below. At time T1, in the changeover switch 48, itsinput terminal is changed from 48b to 48c in synchronism with the fallof synchronous signal SY1. At the same time, in the changeover switch45, its output terminal is changed from the output terminal 45b to 45a,and in the changeover switch 46, its output terminal is changed from 46cto 46b. At this time, the shift register 41 and shift register 42 areconnected to the data bus 47, and data D1 and data D2 of 32 bits eachare applied in parallel in 32 bits or in parallel in 16 bits each. Atthe shift register 43, synchronizing with the clock signal CK1, the dataD0 read into the shift register 43 in the period before time T1 isdelivered bit by bit.

Since the changeover switch 48 is selected at its input terminal 48c asstated above, data D0 is sent out into the transmission line 49 bit bybit. In this way, the data D0 is transmitted as a serial signal. Suchdata transfer is effected in the period from time T1 to time T2 when thesynchronous signal SY1 rises. As a result, the 32-bit data D0 istransferred as a serial signal.

At time T2, when the synchronous signal SY1 rises, in the changeoverswitch 48 synchronously, its input terminal is changed from 48c to 48a.At this time, the changeover switches 45, 46 do not change over, butsince the parallel data is applied to the shift registers 41, 42 fromthe data bus 47, the transfer speed is fast, and when the synchronoussignal SY1 rises at time T2, the data D1, D2 are already stored in theshift registers 41, 42. In such a state, along with reading of the dataD1 from the shift register 41, parallel data will not be applied to thedata bus 47 to the shift register 41.

In the period from time T2 till time T3 when the synchronous signal SY1falls, data D1 is sent out to the transmission line 49 bit by bit.

When the synchronous signal SY1 rises at time T3, in the changeoverswitch 48 synchronously, its input terminal is changed from 48a to 48b.In the changeover switches 45, 46, the respective output terminals arechanged over from 45a, 46b to 45c, 46a. That is, the changeover switch45, in synchronism with the fall of the synchronous signal SY1, itsoutput terminal is changed over

from 45a to 45c to 45b and to 45a, and in the changeover switch 46, insynchronism with the fall of the synchronous signal SY1, its outputterminal is changed over

from 46b to 46a to 46c and to 46b. In the changeover switch 48, insynchronism with the rise and fall of the synchronous signal SY1, itsoutput terminal is changed over

from 48c to 48a to 48b and to 48c.

In this way, in the period of data read-out from any one of the shiftregisters, the data is applied to the other two shift registers from thedata bus 47, and in the period from time T1 to time T3, serial data of64 bits will be led out into the transmission line 49.

In the period from time T3, data D3, D4 are read parallel into the shiftregisters 43, 41 from the data bus 47. The shift register 42 is, at thistime, connected to the transmission line 49, and the data D2 which isits memory content is delivered bit by bit.

Referring next to FIGS. 25 and 26, the operation at the reception sideis explained. To the reception line 54, the serial data as shown in FIG.26 (7) is transmitted. At this time, the changeover switch 51 is changedover in its output terminal as shown in FIG. 26 (5), and the switchingaction of the input terminal at changeover switches 55, 56 becomes asshown in FIG. 26 (3), (4).

In the period from time T1 to time T2, at the changeover switch 51,since its output is selected at 51c, the serial data reaching thereception line 54 is applied to the shift register 59. At the shiftregister 59, the above input serial data is read into inside bit by bitby the clock signal generated inside the transfer register 53. In thisway, the 32-bit data D0 is read into the shift register 59 in the periodfrom time T1 to time T2. Thus, the data D0 is held inside the shiftregister 59 at time T2.

In the period from T1 to T2, the shift registers 57, 58 are connected tothe data bus 60, and the data Da, Db entered in the shift registers 57,58 before time T1 are applied to the data bus 60 in a relatively shorttime after time T1.

In the period from time T2 to time T3, at the changeover switch 51,since the output terminal is selected at 51a, the data D1 which is theserial data reaching the reception line 54 is applied to the shiftregister 57. At this time, in the changeover switch 55, its input isselected at 55a, and the shift register 57 is connected to the data bus60, but since the data Da taken in before time T1 is applied to the databus 60 in a relatively short time after T1, the shift register 57 isready to receive the next data.

At time T3, in the changeover switch 51, its output terminal is changedto 51b, and the input terminals of the changeover switches 55 and 56 arerespectively changed to 55c, 56a. As a result, in a relatively shortperiod after time T3, the data bus 60 is supplied with the data D0, D1held by the shift registers 59, 57 respectively, and the shift register58 with the next data D2, bit by bit.

Thus, in this embodiment, at the transmission side transfer register 44,the data held by the shift registers 41, 42, 43 are selectively sent outbit by bit to the transmission line 49 by the changeover action of thechangeover switch 48. To the remaining two shift registers which are notdelivering data at this time, parallel data is applied from the data bus47 in a relatively short time.

At the transfer register 53 at the reception side, the serial datareaching the reception line 54 is selectively fed to the shift registers57, 58, 59, and the data held by the remaining two shift registers towhich the serial data is not fed is entered to the data bus 60 asparallel data.

As a result, at the transmission side and reception side, theindividually installed registers possess the functions of both bufferregister and transfer register as mentioned in relation to the priorart, so that the number of registers may be reduced to 3/4.

Further, generally, in transfer of group data composed of m word data,2m registers were needed in the prior art, but in the invention only m+1shift registers are needed, and the number of shift registers is reducedto (m+1)/2m. Hence, the structure necessary for data transfer may besubstantially simplified.

According to the invention, thereby, in transferring group data composedof m word data, the equivalent functions as 2m registers needed in theprior art may be realized by m+1 registers only, and the number ofrequired registers is only (m+1)/2m, and the structure for data transfermay be notably simplified. Therefore, the construction will not becometoo large if the data length to be transferred is very large.

FIG. 27 is a block diagram of an embodiment of the invention. The analogsound signals of right and left channels fed to the input terminal 13are converted into a digital sound signal of two channels in theanalog/digital converter circuit 14, and is applied to the processorDSP1 from line 15. In this processor DSP1, the sound signal of twochannels entered through the line 15 is digitally processed, and inorder to enhance the presence as in the surround system, the soundsignals of four channels to be applied to the speakers disposed at thefront left side FL, front right side FR, rear left side RL, and rearright side RR is sent out into a line 16, and is applied to the firstprocessor DSP2 of the invention.

At this processor DSP2, the sound signal of four channels given from theline 16 is further digitally processed, and the 16-bit sound signals atthe front left and right side FL, FR are stored in series into the shiftregister 17, while the sound signals of the rear left and right side RL,RR are stored in the other shift register 18. At the shift register 17,18, the speaker configuration and the corresponding digital soundsignals are indicated by the same reference codes FL, FR; RL, RR.

From a clock signal generator circuit 19, a clock signal having apredetermined frequency shown in FIG. 28 (1) is led out into a line 20,and is applied to the input terminal 21 of the processor DSP2. Thisclock signal is applied to a control circuit 22 provided in theprocessor DSP2. This control circuit 22, responding to the clock signalapplied to the input terminal 21, leads out the signal indicated in FIG.28 (2) to the line 23, while a signal shown in FIG. 28 (2) possessing aninverted waveform of the signal from the line 23 is sent out to a line24. Another control circuit 25 receives signals from the lines 23, 24,leads out a signal shown in FIG. 28 (4) to a line 26, and also sends outa signal shown in FIG. 28 (5) to a line 27. The signals led out from thelines 26, 27 are synchronized with the clock signal applied to the inputterminal 21, and the signals led out from these lines 26, 27 arewaveforms of mutually reverse polarity.

The signal sent out from the line 26, is applied to the shift register17, and is also applied to the AND gate G1. The signal led out from theline 27 is applied to the shift register 18, and is also added to theother AND gate G2. The shift register 17, responding to the signal fromthe line 26 as shown in FIG. 28 (6), sequentially leads out the soundsignals of 16 bits each of the front left and right side FR, FL storedthere bit by bit. Likewise, the shift register 18, responding to thesignal from line 27, sequentially leads out the sound signal of 16 bitseach of the rear left and right side RL, RR, bit by bit as shown in FIG.78 (7). In FIG. 28 (6), FL1 to FL6 denote the data of the first to sixthbit of the sound signal of the front left side FL, and in FIG. 28 (7),similarly, RL1 to RL5 represent the data of the first to fifth bit ofthe sound signal of the rear left side RL.

The sound signals of every bit from the shift registers 17, 18 areapplied to AND gates G1, G2. The sound signals from AND gates G1, G2 areapplied to two second digital signal processing circuits, digital/analogconverter circuits 30, 31, respectively through output terminal 28 andline 29 from the OR gate G3. The digital signal led out from outputterminal 28 is as shown in FIG. 28 (8). In this way, responding to theclock signal applied to the input terminal 21, the sound signals storedin the shift registers 17, 18 are led out from the output terminals 28,bit by bit alternately, serially and sequentially. The changeover meansis composed by comprising the AND gates G1, G2.

The clock signal from the clock signal generator circuit 19 is directlyapplied from the line 20 to the digital/analog converter circuit 30, andis also applied to another digital/analog converter circuit 31 by way ofan inverter circuit N1. The digital/analog converter circuits 30, 31have identical structures. The digital/analog converter circuit 30,responding to the rise of the clock signal indicated in FIG. 28 (1)through line 20, receives and stores the sound signal through line 29bit by bit. Therefore, the digital/analog converter circuit 30 receivesonly the sound signal stored in the shift register 17 indicated byreference codes FL1, FL2, FL3, . . . , among the digital sound signalson the line 29 indicated in FIG. 28 (8), bit-sequentially, and convertsit into an analog sound signal of two channels in total of the frontleft and left side FL, FR, and leads it out.

The other digital/analog converter circuit 31, responding to the rise ofclock signal through the inverter circuit N1, receives only the soundsignal stored in the shift register 18 as indicated by RL1, RL2, RL3, .. . , among the sound signals shown in FIG. 28 (8), bit-sequentially,and converts it into an analog sound signal in a total of two channelsof rear left and right side, RL, RR, and leads it out.

In this way, the sound signal from the output terminal 28 of theprocessor DSP2 is commonly given to the two digital/analog convertercircuits 30, 31 connected after the line 29, and the clock signal fromthe clock generator circuit 19 is applied to these circuits DSP2; 30, 31directly and by way of inverter circuit N1 to control. Therefore, thestructure may be simplified.

The invention may be embodied not only for processing of sound signal,but also widely in other technical fields. Further, instead of thedigital/analog converter circuits 30, 31, other circuits for digitalsignal processing may be used.

The invention enables, as is clear from the description herein, thetransfer of output data from a first processor to two second processorsalternately, and in a simple structure.

FIG. 29 is a block diagram showing a structure of a sound signalprocessor 41 in an embodiment of the invention. For example, an analogsound signal from a radio receiver is given to an analog/digitalconverter 46 from an input terminal 45, and is converted into a digitalsignal, and is fed into a digital signal processor (hereinafter calledprocessor) 44 composed of large-scale integration or the like.

The processor 44 controls the tone, or processes echo or sound signals,for example, by performing arithmetic calculations of input signals suchas addition and multiplication, or delaying. The output of the processor44 is applied to the processor 48 for a different arithmetic processing,and is applied to the digital/analog converter 52 to be converted intoan analog signal, which is given to a power amplifier circuit or thelike by way of output terminal 53.

The output of the analog/digital converter 46 is composed of 16 bitseach of right and left channels per sampling period, in a total of 32bits of fixed decimal point data as shown in FIG. 30 (1). Digital signalprocessors 44, 48, analog/digital converter 46, and digital/analogconverter 52 perform arithmetic operation on the basis of the clocksignal SCLK from a clock generator 54 shown in FIG. 30 (2) andsynchronous signal SYNC shown in FIG. 30 (3). At the processors 44, 48,in order to suppress deterioration of dynamic range or S/N ratio due tooverflow or underflow during arithmetic operation, the sound signal datais floating decimal point data composed of 16-bit mantissa data shown inFIG. 30 (4) and 4-bit exponent data shown in FIG. 30 (5), and arithmeticoperation and transfer are carried out accordingly.

FIG. 31 is a diagram to show the conversion action of the fixed decimalpoint data and floating decimal point data. The input signal to theprocessor 44 is 32-bit fixed decimal point data per sampling period asmentioned above. The processor 44 calculates this input signal intofloating decimal point data, and stores the result of calculation in themantissa transmitting registers 61, 62 of 16 bits for each and exponenttransmitting registers 63, 64 of 16 bits for each provided each forright and left channels. Thus stored data are processed arithmetically,in the processor 44, as 20-bit floating decimal point data per channelas indicated by reference code 81, 82.

The data stored in the mantissa transmitting registers 61, 62, andexponent transmitting registers 63, 64 are transferred from inputterminals 73, 74 of the processor 48 to mantissa receiving registers 67,68 and exponent receiving registers 69, 70, through lines 65, 66 fromoutput terminals 71, 72 provided separately for each one of registers61, 62; 63, 64. The mantissa data transferred through the line 65 isshown in FIG. 30 (4), and the exponent data transferred through line 66is shown in FIG. 30 (5). The processor 48, after arithmeticallyprocessing the transferred data as floating decimal point data of 20bits per channel of right and left as shown by reference codes 83, 84,converts into fixed decimal point data and applies to the digital/analogconverter 62.

The mantissa data stored thus in the mantissa transmitting registers 61,62 is transferred to the mantissa receiving registers 67, 68 throughline 65, while the exponent data stored in the exponent transmittingregisters 63, 64 is transferred to the exponent receiving registers 69,70 through line 66, so that the mantissa data and exponent data may betransferred in parallel. Without using special converter circuitry suchas bit number converting circuits 25, 29 as mentioned in relation to thebackground technology, it is possible to process arithmetically ortransfer by using clock signals common with the analog/digital converter46 and others, so that the structure may be simplified.

Thus, according to the invention, since the mantissa portion andexponent portion of the floating decimal point data are stored in theseparate registers, it is possible to process arithmetically andtransfer by synchronously controlling both registers by a common clocksignal, and the structure may be simplified at the same time.

FIG. 32 is a block diagram showing a construction of an embodiment ofthe invention, in which the data is transferred by the data transfermethod of the invention between processors DSP3, DSP4.

The processors DSP3, DSP4 are similar in structure, and the structure ofthe processor DSP3 is explained below.

If the signal entering the processor DSP3 is fixed decimal point data,this fixed decimal point data is entered from line 7 as a serial signal.If the data entering the processor DSP3 is floating decimal point data,the exponent portion of the floating decimal point data is entered fromline 7, and the exponent portion of the floating decimal point data isentered from line Pa as a parallel signal. The serial signal of line 7is applied to the mantissa receiving register 11, and the parallelsignal of line Pa is applied to the exponent receiving register 12. Thedata in the mantissa receiving register 11 is entered in the mantissaregister 13a of the register 13, while the data in the exponentreceiving register 12 is fed into the exponent register 13b of theregister 13 similarly.

The data in the mantissa register 13a and exponent register 13b areapplied to an internal bus 16 by way of gates 14a and 14b, respectively.These data are applied from the internal bus 16 to the memory circuit(not shown), etc. A processing circuit 15 arithmetically processes suchdata.

If the result of arithmetic processing in the processor DSP3 is fixeddecimal point data, the fixed decimal point data as the result ofarithmetic processing is entered from the internal bus 16 into themantissa register 18a through gate 17a. This fixed decimal point data isapplied to the mantissa transmitting register 19 of the mantissaregister 18a. The data of this mantissa transmitting register 19 istransferred to the processor DSP4 as a serial signal through line 8.

If the result of arithmetic processing at the processor DSP3 is floatingdecimal point data, the mantissa portion and exponent portion of thefloating decimal point data which is the result of calculation aredelivered to the mantissa register 18a and exponent register 18b of theregister 18 respectively through gates 17a, 17b from internal bus 16.

The data of the mantissa register 18a is applied to the exponenttransmitting register 19. The data in the exponent register 18b isapplied to the exponent transmitting register 20.

The mantissa portion of the floating decimal point data which is theresult of arithmetic processing at the processor DSP3 is transferredfrom the mantissa transmitting register 19 to the processor DSP4 as aserial signal through line 8, and the exponent portion of the floatingdecimal point data is transferred to the processor DSP4 through line Pbas a parallel signal from the exponent transmitting register 20.

At the processor DSP4, the serial signal of line 8 is entered into themantissa receiving register 21, and the parallel signal of line Pb isentered into the exponent receiving register 22. Afterwards, afterarithmetic processing, as in the case of processor DSP3, the result ofarithmetic processing is led out into lines 9 and Pc from the mantissatransmitting register 29 and exponent transmitting register 30.

To the processors DSP3, DSP4, synchronous clock signal SYNC and serialclock signal SCK for transferring the data synchronously are applied.

FIGS. 33 (1)-(4) are waveform diagrams for explaining the data transferoperation between the processors DSP3, DSP4, and the followingexplanation is made by reference to this diagram.

The synchronous signal SYNC entered in the processor DSP3 is shown inFIG. 33 (1). From rise or fall of the synchronous signal SYNC, datatransfer of one of the serial signals is started, and upon rise of theserial clock signal SCK shown in FIG. 33 (2), the serial signal of line7 shown in FIG. 33 (3) is latched.

Upon a next fall or rise of synchronous signal SYNC, one data transferof serial signal is terminated, and a next data transfer is started. Atthis time, the data of serial signal expresses the fixed decimal pointdata when the processor DSP3 delivers fixed decimal point data, andrepresents the mantissa portion of the floating decimal point data whenit delivers floating decimal point data.

When the processor DSP3 delivers floating decimal point data, theexponent portion of the floating decimal point data is led out as aparallel signal shown in FIG. 33 (4) to the line Pb, and at theprocessor DSP4, this parallel signal is latched upon the rise and fallof the synchronous signal SYNC.

In this embodiment, thus, the transfer at the serial port for datainput, output is effected similarly by same serial clock signal whetherthe data is fixed decimal point data or floating decimal point data.Therefore, at the processors DSP3, 4, it is possible to distinguish thefixed decimal point data from floating decimal point data by detectingthe presence or absence of exponent portion by the software, so that thestructure of processor may be simplified. Further, as compared with theparallel transfer of all these data transfers, for example, the numberof conductors for input and output can be decreased, and the wiring maybe simplified. Furthermore, if the data format differs between input andoutput, only one kind of frequency is enough for serial clock signal,and the composition of the clock signal generator may be simplified.

In this embodiment, as the parallel port for input and output of themantissa portion of the floating decimal point data, a general-purposeparallel port may be used, or when an exclusive parallel port isprovided, this parallel port may be used as the input, output port ofother data when inputting or outputting fixed decimal point data.

FIG. 34 is a further practical embodiment of the invention, andcorresponding parts to those mentioned in the foregoing embodiments areidentified with same reference codes.

In this embodiment, data is transferred between an analog/digitalconverter AD2 and processor DSP3, between processors DSP3 and DSP4, andbetween processor DSP4 and a digital/analog converter DA2.

An analog signal, for example, an acoustic signal is entered from line 6into the analog/digital converter AD2. From the analog/digital converterAD2, a digital signal of fixed decimal point data having a data lengthof, for example, 16 bits is delivered from line 7 into processor DSP3.Data transfer from the analog/digital converter AD2 to processor DSP3 iseffected synchronously by the serial clock signal SCK and synchronoussignal SYNC delivered from the clock signal generator CK2.

The fixed decimal point data entered in the processor DSP3 isarithmetically processed, and floating decimal point data possessing,for example, 16-bit mantissa portion and 3-bit exponent portion isdelivered. As stated above, the mantissa portion of the floating decimalpoint data is applied to the processor DSP4 through line 8, and theexponent portion of the floating decimal point data is applied to theprocessor DSP4 through line Pb. In the data transfer of this case, too,as in the data transfer from the analog/digital converter AD2 toprocessor DSP3, the data is transferred synchronously by the serialclock signal SCK from the clock signal generator CK2 and synchronoussignal SYNC.

The floating decimal point data entered in the processor DSP4 isarithmetically processed, and is converted into fixed decimal pointdata. This fixed decimal point data is delivered to the digital/analogconverter DA2 through line 9. In this data transfer also, data istransferred synchronously by the serial clock signal SCK from the clocksignal generator CKS and synchronous signal SYNC. At the digital/analogconverter DA2, the input fixed decimal point data is converted into ananalog signal, and is led out to line 10.

When transferring the acoustic signal after analog/digital conversion asin this embodiment, the output from the analog/digital converter circuitand the input to the digital/analog converter circuit are usually fixeddecimal point data, and the data transfer between processors is carriedout by the floating decimal point data. When the data transfer method ofthe invention is employed in such case, if the data format differsbetween the input and output at the processors DSP3, DSP4, data can betransferred by the same serial clock signal, and the structure of theprocessor may be simplified, and all data can be transferred by only onekind of serial clock signal. Therefore, the wiring may be simplified,and complicated circuit composition such as digital phase-locked loop isnot needed for the purpose of generation of clock signal.

As explained herein, in the data transfer method of the invention,transfer of fixed decimal point data in the same format as the mantissaportion of floating decimal point data, for example, may be similarlyeffected by a synchronous signal same as the floating decimal pointdata, by using the mantissa registers of the processor.

Therefore, both fixed decimal point data and floating decimal point datacan be transferred in a simple structure.

FIG. 35 is a block diagram of an embodiment of the invention. Analogsound signals of right and left channels are fed into the analog/digitalconverter AD2 from line 11, and the fixed decimal point data is appliedto the processor DSP4 for the portion of two channels. This processorDSP4 arithmetically processes the sound signal which is the two-channelfixed decimal point data, and produces floating decimal data. The signalfrom the processor DSP4 is transmitted from the mantissa transmittingregister A11 and exponent transmitting register B11 through lines 15,16, and is applied to the mantissa receiving register A12 and exponentreceiving register B12 of the other processor DSP5.

At the processor DSP5, various floating decimal point data processingsare carried out, and finally they are converted into fixed decimal pointformat, and the sound signal data for four channels for four speakers 2are stored in the mantissa transmitting register A13, and the fixeddecimal point data which is the sound signal for a superwoofer 3 isstored in the exponent register B13.

The signal from the mantissa transmitting register A13 is stored in theregister A14 of the digital/analog converter DA3 from line 12, and thesound signals for the portion of four channels are converted into analogsound signals as fixed decimal point data. To the low pass filter 4provided thus for each channel, analog sound signals are applied, andthe output from this low pass filter 4 is amplified by the amplifiercircuit 5, and the speakers 2 are driven.

The sound signal for the superwoofer 3 from the exponent transmittingregister B13 of the processor DSP5 is applied from line 13 toserial/parallel converter 14 to be converted into parallel bit signals,which are sent into digital/analog converter DA4 to be converted intoanalog signal. The analog sound signal from this digital/analogconverter DA4 is applied to the amplifier circuit 7 through low passfilter 6, and the superwoofer 3 is driven.

FIG. 36 is a block diagram showing a composition relating to processorsDSP4, DSP5, digital/analog converter DA3, and registers X1 to X7, A11 toA14, B11 to B13 of serial/parallel converter 14. The two-channel soundsignal data which is the fixed decimal point data from theanalog/digital converter AD2 is fed into the receiving register X1 inthe processor DSP4 through line 41.

The data thus input is two-channel fixed decimal point data, and is fedinto store regions N1, N2 of receiving register X1, while the remainingstore regions N3, N4, and store regions H1 to H4 of receiving registerX2 are empty. When the data input is complete, the empty store regionsN3, N4; H1 to H4 are handled as 0, and the contents in the store regionsN1 to N4 of receiving register X1 are stored in the store regions R1 toR4 of the register X3, while the contents in the store regions H1 to H4of receiving register X2 are stored in the store regions R1 to R4 of theregister X3. At this time, the fixed decimal point data is convertedinto the floating decimal point data at the exponent portion 0.

A processing circuit 29 reads out these data through gates 42, 43, anddata bus 17, and various floating decimal point arithmetic processingssuch as tone control are effected to the two-channel sound signal(floating decimal point data) by using the data of a memory (not shown),and four-channel floating decimal point data is created, which is storedin the register X4 through gates 44, 45.

The register X4 can store a total of four sets of floating decimal pointdata, and the mantissa portion of the floating decimal point data isindicated by reference codes L1 to L4, and the exponent portion isindicated by M1 to M4. For example, the first floating decimal pointdata is composed of mantissa portion L1 and exponent portion M1, andthese floating decimal point data M1, L1; M2, L2; M3, L3; M4, L4 aresound signals for four channels. The mantissa portions L1 to L4 storedin the register X4 are respectively stored in the store regions C1 to C4of the mantissa transmitting register A11. The exponent portions M1 toM4 are respectively stored in the store regions D1 to D4 by the exponenttransmitting register B11. Each one of mantissa portions L1 to L4 iscomposed of 16 bits, and each one of exponent portions M1 to M4 is 4-bitdata.

The contents in the store regions C1 to C4 of the mantissa transmittingregister A11 are transferred to the store regions E1 to E4 respectivelyof the mantissa receiving register A12 of the processor DSP5 throughline 15. Likewise, the contents in the store regions D1 to D4 of theexponent transmitting register B11 are transferred to store regions Flto F4 of the exponent receiving register B12 through line 16,respectively. The store contents in the mantissa receiving register A12and exponent receiving register B12 are fed into the register X5.

The register X5 possesses the regions for receiving four sets offloating decimal point data, and the mantissa portions P1 to P4 andexponent portions Q1 to Q4 of each one of floating decimal point dataare stored in the unit of floating decimal point data. The processingcircuit 24 of the processor DSP5 reads out the data, when the input ofthe data is complete, from the register X5 through the gates 45, 46, andthe floating decimal point arithmetic processings are effected again,and the results are added to the four-channel sound signal data, and thesound signal data for one-channel superwoofer 3 is obtained. Sucharithmetic processing is carried out by using the data stored in thememory (not shown) provided in the processor DSP5, and the one-channelfloating decimal point data (the sound signal for the superwoofer 3 inthis embodiment) is obtained additionally.

These data are stored in the register X6 by way of data bus 23 and gates47, 48. The register X6 possesses the region for receiving four sets offloating decimal point data, and the mantissa portions T1 to T4 andexponent portions U1 to U4 of the floating decimal point data are storedin the unit of floating decimal point data.

Here, since the digital/analog converters DA3, DA4 handle the fixeddecimal point data, finally five sets of floating decimal point data,that is, four sets of floating decimal point data expressing soundsignals for four channels, and the floating decimal point dataexpressing the sound signal for the superwoofer 3 are converted intofixed decimal point data, and the data for four channels are stored inthe register for mantissa A13, and the data for superwoofer 3 for onechannel is stored in the register for exponent B13, and are transferredto the receiving register A14 of the digital/analog converter DA3, andthe receiving register X7 of the serial/parallel converter 14 which isthe interface circuit for the digital/analog converter DA4.

FIGS. 37 (1)-(4) are waveform diagrams for explaining the operation ofthe constitution shown in FIG. 36. From the clock signal generator 25 tothe line 26, a control signal SYNC shown in FIG. 37 (1) is led out, anda control signal SCLK shown in FIG. 37 (2) is led out to the line 27. Inone period from the fall of the control signal SYNC to the next trailingedge, the bit-sequential data from the mantissa transmitting registerA11 is sequentially transferred to the line 15 as shown in FIG. 37 (3).In the period when the control signal SYNC is at a low level, thebit-sequential data from the exponent transmitting register B11 is ledout to the line 16 as shown in FIG. 37 (4), and is transferred. In thisway, the mantissa transmitting register A11 and exponent transmittingregister B11 deliver outputs independently, and are controlled insynchronism by the control signals SYNC, SCLK which are common clocksignals. This holds true with the mantissa receiving register A12 andexponent receiving register B12, and also with the registers A13, A14,B13, X7.

The exponent portion has 4 bits in the above embodiment, and 16-bitsound signal is transferred for the superwoofer 3 from the processorDSP5, but as another embodiment of the invention it may be also possibleto process the sound signal in 8 bits, for example, for the superwoofer3 by using the exponent portion.

FIG. 38 is a block diagram of a different embodiment of the invention,which is similar to the foregoing embodiment, and corresponding partsare identified with same reference codes. Of note in this embodiment isthat the floating decimal point data is bit-sequentially transferred bysingle data lines 30, 31. In this embodiment, the data is transferred inthe common lines 30, 31 by the mantissa portion and exponent portion ofthe floating decimal point data, but by controlling this transfertiming, the mantissa portion and exponent portion are distinguished atthe transmitting and receiving sides, and are separately stored in theregisters, so that the sound signals for four channels and the soundsignal for the superwoofer 3 may be arithmetically processed, and used.Moreover, by using the 4-bit sound signal of each channel from theexponent transmitting register B13 by two each, it is also possible toprocess the sound signal for the speaker of another channel indicated byreference code 3a, aside from the superwoofer 3 mentioned above. Theconstituent elements relating to the speaker 3a are indicated by brokenlines, and the constitution for the superwoofer 3 is indicated by thesubscript a.

The invention may be embodied not only in processing of sound signal,but also widely in other technical fields.

Thus, according to this invention, eliminating the in the circuitcomposition, the cost may be reduced unneeded processing apparatus.

FIG. 39 is a block diagram showing the configuration near processor DSP4in an embodiment of the invention. The processor DSP4 is composed ofmantissa receiving register A10 and mantissa transmitting register A11which are mantissa registers, and exponent receiving register B10 andexponent transmitting register B11 which are exponent registers, and isdesigned to transfer data with a similarly composed processor DSP5.

For example, an analog signal such an acoustic signal is fed from line11 into analog/digital converter AD2 to be converted into a digitalsignal. This digital signal is usually fixed decimal point data, andpossesses a data length of, for example, 16 bits. This fixed decimalpoint data is delivered from the transmitting register A9 of theanalog/digital converter AD2 into the mantissa receiving register A10 ofthe processor DSP4.

To the exponent receiving register B10 of the processor DSP4, a signal,for example, from a potentiometer 1 for detecting fluctuations inexternal voltage is entered after being converted into a digital signalof low bits, such as 3 bits, in the analog/digital converter AD1. Thedata in the mantissa receiving register, A10 and exponent receivingregister B10 are applied to the internal bus D1 by way of mantissaregister C1a and exponent register C1b of the internal register C1.

At the processor DSP4, according to the data from the exponent registerC1b, the data from the mantissa register C1a is arithmeticallyprocessed, and the floating decimal point data is obtained as the resultof this calculation. The mantissa portion and exponent portion of thisfloating decimal point data are delivered to the mantissa transmittingregister A11 and exponent transmitting register B11 through the mantissaregister C1a and exponent register C1b of the internal register C1.

The data in the mantissa transmitting register A11 and exponenttransmitting register B11 of the processor DSP4 are transferred to themantissa receiving register A12 and exponent receiving register B12 ofthe processor DSP5 through lines 15, 16 respectively, and the floatingdecimal point data is thus transferred between the processors DSP4,DSP5.

At the processor DSP5, the floating decimal point data in the mantissareceiving register A12 and exponent receiving decimal register B12 aresent into the internal bus D2 through the mantissa register C2a andexponent register C2b of the internal register C2 to be processedarithmetically. If this result of calculation is, for example, fixeddecimal point data, the fixed decimal point data from the internal busD2 is applied to the mantissa transmitting register A13 through themantissa register C2a of the internal register C2. The output from themantissa transmitting register A13 is applied to the digital/analogconverter or the like through the line 12.

At this time, if the result of calculation obtained by a differentprocessing from the floating decimal point data of the mantissareceiving register A12 and exponent receiving register B12 is entered inthe exponent transmitting register B13, it may be designed to deliverthe signal from the line 13 through the exponent transmitting registerB13.

In this embodiment, since it is designed to process arithmetically atthe processor DSP4 according to the data entered in the exponentreceiving register B12 through the analog/digital converter AD1 from thepotentiometer 1, the configuration shown in FIG. 39 may be applied, forexample, in the linear control such as volume control and open loopadaptive control.

FIG. 40 is a diagram to explain the operation when a function of anelectronic volume control is added to the processor DSP4. Fixed decimalpoint data representing an acoustic signal is led out from theanalog/digital converter AD2 to the line 14, while the signal from thepotentiometer 1 is converted into a digital signal by the analog/digitalconverter AD1 and is led out into the line 10.

At the processor DSP4, as shown in FIG. 40, the data from the line 14 isdigitally amplified at an amplification factor according to the datafrom the line 10, and is delivered. In this way, the acoustic signal canbe controlled to a desired volume level by the potentiometer 1.

FIG. 41 is a block diagram showing a different embodiment of theinvention, and the parts corresponding to those in the foregoingembodiment are identified with same reference codes.

In this embodiment, the signal entered in the exponent receivingregister B10 of the processor DSP4 is a control command of the processorDSP4. The signal to represent the control command of the processor DSP4is entered in a flag generator 2, and a flag to show a control commandis entered in the exponent receiving register B10 through line 10 fromthe flag generator circuit 2.

The exponent portion of the floating decimal point data is generally oflow bits, but its data length is sufficient as the flag of command forcontrolling the processor DSP4 externally, and it may be used whenchanging over the operation program of the processor DSP4 by force, forexample.

In this way, the processor DSP4, when entering the fixed decimal pointdata of, for example, analog/digital converter, enters the fluctuationsof external power source or control command by effectively utilizing,without any waste, the input terminal of the exponent portion offloating decimal point data or exponent receiving register B10.Therefore, the processor can process the data at higher speed, and theapplication range of the processor is expanded.

In this embodiment, as the port for input and output of the processorDSP4, the serial port and general-purpose parallel port usuallypossessed by the processor may be utilized as for the mantissa portionof the floating decimal point data, fixed decimal point data, andexponent portion of floating decimal point data.

According to the invention, as is clear from the description herein,when fixed decimal point data in the same format as the mantissa portionof floating decimal point data is entered in, for example, theprocessor, the fixed decimal point data is stored in the mantissaregister, and other data may be entered and stored in the exponentregister.

Therefore, waste in the construction of the processor may be eliminated,and more advanced data processing making full use of the functions ofthe processor may be realized.

FIG. 42 is a block diagram showing a composition of an acoustic signalprocessor 21 in an embodiment of the invention. For example, an analogacoustic signal from a radio receiver is applied to an analog/digitalconverter 23 from an input terminal 22 to be converted into a digitalsignal, and is fed into a processor 24 realized by large scaleintegration.

The processor 24 arithmetically processes the input signal by addition,multiplication or the like, or by delay operation, and processes theacoustic signal for tone control or echo. The output of the processor 24is applied to a processor 25 for another arithmetic processing, and isapplied to digital/analog converters 26, 27 to be converted into analogsignal, which is given to a power amplifier circuit or the like fromoutput terminals 28 and 29.

The output of the analog/digital converter 23 is, as shown in FIG. 43(1), composed of a total of 32 bits of fixed decimal point data, of 16bits each of right and left channels per sampling period. The processors24, 25, analog/digital converter 23, and digital/analog converters 26,27 operate arithmetically on the basis of clock signal SCLK from clockgenerator circuit 30 shown in FIG. 43(2), and synchronous signal SYNCshown in FIG. 43 (3).

FIG. 44 is a block diagram showing an internal structure of processors24, 25. The processors 24, 25 are identical in structure, and for thesake of simplicity, in FIG. 44, only the transmission system is shown asthe processor 24 and only the reception system is given as the processor25. The input signal to the processors 24 is, as stated above, 32-bitfixed decimal point data per sampling period.

Here, in order to inhibit deterioration of dynamic range or S/N ratiodue to overflow or underflow at the time of arithmetic processing, whenusing the processors 24, 25 for use in transfer of floating decimalpoint data, the processor 24 converts this input signal into floatingdecimal point data, and stores. Thus stored data is, in the processor24, arithmetically processed as floating decimal point data of 20 bitseach of right and left channels as indicated by reference codes 35, 36.The data in 16-bit mantissa regions B1, B3 are stored in 16-bit mantissatransmitting registers 31, 32, and the data in 4-bit exponent regionsB2, B4 are stored in 4-bit regions A1, A2 of 16-bit exponenttransmitting registers 33, 34.

The data stored in the mantissa transmitting registers 31, 32 andexponent transmitting registers 33, 34 are transferred from the outputterminals 51, 52 individually provided for registers 31, 32, 33, 34, to4-bit regions C1, C2 of 16-bit mantissa registers 41, 42 and 16-bitexponent receiving registers 43, 44 from input terminals 61, 62 of theprocessor 25 through lines 71, 72.

At this time, the mantissa data transferred through line 71 is indicatedin FIG. 43 (4), and the exponent data transferred through line 72 isindicated in FIG. 43 (5). At the processor 25, the transferred data isarithmetically processed as 20-bit floating decimal point data each ofright and left channels composed of 16-bit mantissa portion and 4-bitexponent portion as shown by reference codes 45, 46, and is convertedinto fixed decimal point data of two channels each of 16 bits of eachchannel (total 4 channels), and is applied to the digital/analogconverters 26, 27.

On the other hand, in order to transfer multiple data simultaneouslybetween processors 24 and 25, if slightly lowering the precision, whenthe processors 24, 25 are used for transfer of fixed decimal point data,the processors 24 converts the input signal of fixed decimal point datainto floating decimal point data, and processes arithmetically, andconverts into fixed decimal point data, and the result of this operationis stored in 16-bit mantissa transmitting registers 31, 32 provided forright and left channels. Meanwhile, the exponent transmitting registers33, 34 store the fixed decimal point data aside from 16 bits of rightand left channels indicated by reference codes 37, 38. In this case,too, the operation is the same as in the above case in that thearithmetic processing is carried out after converting into floatingdecimal point data of 20 bits each of right and left channels in theprocessor 24.

The data stored in the mantissa transmitting registers 31, 32 andexponent transmitting registers 33, 34 are transferred to the mantissareceiving registers 41, 42 and exponent receiving registers 43, 44through lines 71, 72, as in the above case. At this time, the fixeddecimal point data transferred through the line 71 is indicated in FIG.43 (6), and the other fixed decimal point data transferred through theline 72 is indicated in FIG. 43 (7). They are both 16-bit fixed decimaldata per channel (32 bits per sampling period).

The processor 25 arithmetically processes the transferred fixed decimalpoint data as 20-bit floating decimal data each of right and leftchannels, and processes in the same manner as the processor 24 toconvert into fixed decimal point data of two channels each of right andleft of 16 bits per channel (total 4 channels), and sends intodigital/analog converters 26, 27 in every data per sampling period.

In this way, since the exponent registers 33, 34, and 43, 44 are of thesame big length (16 bits in this embodiment) as the mantissa registers31, 32, and 41, 43, when transferring fixed decimal point data betweenprocessors 24 and 25, it is possible to transfer simultaneously theother 16-bit fixed decimal point data of right and left channels byusing the exponent registers 33, 34, and 43, 44, so that the transfercapacity is twice as much as in the prior art. Moreover, between theprocessor 25 and the digital/analog converters 26, 27, since fixeddecimal point data of two channels each of 16 bits per channel can betransferred simultaneously, it is extremely effective when applying theacoustic signal processor 21 in a processor for a four-channel stereoaudio appliance.

In the invention, therefore, since the exponent registers are set in thesame bit length as the mantissa registers, it may be effectively used inprocessing of floating decimal point data and fixed decimal point data,so that multiple data can be transferred.

FIG. 45 is a block diagram showing a structure of an acoustic signalprocessor 21 in an embodiment of the invention. For example, an analogacoustic signal from a radio receiver is sent into an analog/digitalconverter 23 from an input terminal 22, and is converted into a digitalsignal, which is sent into a processor 24 realized by large scaleintegration or the like.

The processor 24 processes this input signal by addition, multiplicationor other arithmetic operation or delay operation, and processes theacoustic signal such as tone control and surround. The output of theprocessor 24 is applied to a processor 25 for other arithmeticprocessing, and is applied to a digital/analog converter 26 to beconverted into an analog signal, which is applied to a power amplifieror the like through output terminal 27.

The output of analog/digital converter 23 is composed of a total of 32bits of fixed decimal point data of 16 bits each of right and leftchannels per sampling period as shown in FIG. 46 (1). The processors 24,25, analog/digital converter 23, and digital/analog converter 26 processarithmetically on the basis of the clock signal SCLK from clockgenerator 28 shown in FIG. 46 (2) and synchronous signal SYNC shown inFIG. 46 (3).

The processor 24, 25, in order to inhibit deterioration of dynamic rangeof S/N ratio due to overflow or underflow at the time of processing,process arithmetically and transfer as floating decimal point data.Further, the mantissa portion of the floating decimal point data handledin the processor 24, 25 is set in a longer bit length (18 bits in thisembodiment) than the bit length (16 bits) of the fixed decimal pointdata handled externally in order to reduce operational errors andenhance the precision.

FIG. 47 is a block diagram showing an internal structure of processors24, 25. The processors 24, 25 are identical in structure, and for thesake of simplicity, in FIG. 47, only the transmission system is shown asthe processor 24 and only the reception system as the processor 25. Theinput signal to the processor 24 is 32-bit fixed decimal point data persampling period as mentioned above.

The processor 24 receives this input signal by 16-bit mantissa receivingregister (not shown) each of right and left channels. At this time, theexponent receiving register (not shown) composed of 2-bit mantissaregion and 6-bit exponent region is not provided with data and is empty.When the input into the mantissa receiving register is complete, theempty register is handled as 0, and the 16-bit fixed decimal point dataeach of right and left channels from the analog/digital converter 23 isconverted into 24-bit floating decimal point data each of right and leftchannels composed of 18-bit mantissa portion and 6-bit exponent portion,and is processed arithmetically. The configuration of the receptionsystem of the processor 24 is the same as that in the processor 25, ofwhich details are described below.

The arithmetically processed floating decimal point data is stored inbuffer registers 35, 36 for transfer of 24 bits each for right and leftchannels from data bus 39 through gates 37, 38. At this time, the 18-bitmantissa data of each channel is stored in regions A1, C1, D1, andregions A2, C2, D2, while the 6-bit exponent data is stored in region B1and region B2. Of the 18-bit mantissa data, the data of upper 16 bitscomposed of 1-but sign bit expressing the polarity stored in regions A1,A2 and 15-bit data stored in regions C1, C2 is stored in the shiftregisters 31, 32 for mantissa transmission of 16 bits each. Further, the6-bit exponent data stored in regions B1, B2 and the lower 2-bitremaining mantissa data stored in regions D1, D2 are respectively storedin shift registers 33, 34 for exponent transmission of 8 bits each.

The data stored in the mantissa transmitting registers 31, 32, andexponent transmitting registers 33, 34 are transferred through lines 71,72 from the output terminals 51, 52 individually provided for registers31 and 32, 33 and 34 on the basis of the common clock signal SCLK andsynchronous signal SYNC, to 16-bit exponent receiving registers 41, 42,and 8-bit exponent receiving registers 43, 44, from input terminals 61,62 of the processor 25. Incidentally, the data is stored in the bufferregisters 35, 36 at arbitrary timing, and data transfer from the bufferregisters 35, 36 to the mantissa transmitting registers 31, 32 and toexponent transmitting registers 33, 34 is effected, for example, afterevery termination of data transfer from the mantissa transmittingregisters 31, 32. The mantissa data transferred through the line 71 isindicated in FIG. 46 (4), and the exponent data and remaining mantissadata transferred through the line 72 is shown in FIG. 45 (5). Thecontents of the registers 41, 42, 43, 44 are stored in the bufferregisters 45, 46 for transfer upon every termination of data transfer tothe mantissa receiving registers 41, 42 and exponent receiving registers43, 44. At this time, of the data transferred to the mantissa receivingregisters 41, 42, sign bits of 1 bit each are stored in regions A3, A4of buffer register 45, 46, and the mantissa data of the remaining 15bits each are stored in regions C3, C4 of the buffer registers 45, 46.Of the data transferred to the exponent receiving registers 43, 44, theexponent data of 6 bits each are stored in regions B3, B4 of bufferregisters 45, 46, and the remaining mantissa data of 2 bits each arestored in regions D3, D4 of buffer registers 45, 46. The floatingdecimal point data of 24 bits each of right and left channels stored inthe buffer registers 45, 46 are read out through gates 47, 48 atarbitrary timing, and are transferred through the data bus 49, and areprocessed arithmetically by an arithmetic processing circuit (notshown).

The floating decimal point data of 24 bits of each channelarithmetically processed are converted into data expressed only by themantissa portion of 18 bits while the exponent portion is all 0, thatis, fixed decimal point data. In the 18-bit mantissa data, the upper 16bits are stored in the mantissa transmitting register (not shown) asmentioned above, and the 6-bit exponent data of all 0 and the remainingmantissa data of lower 2 bits are stored in the exponent transmittingregister (not shown), and the 16-bit mantissa data stored in themantissa transmitting register is transferred to the digital/analogconverter 26 in the lower stage as 16-bit fixed decimal point dataaccording to the clock signal SCLK and synchronous signal SYNC. In thisway, part of mantissa portion (in this embodiment, data of upper 16 bitseach) in the floating decimal data is stored in the mantissa registers31, 32 and 41, 42, whereas the exponent portion (data of 6 bits each inthis embodiment) and the remaining portion of mantissa (lower 2 bits)are stored in the exponent registers 33, 34, and 43, 44, and terminals51, 52, and 61, 42 are provided in order to enter and deliver thecontents in the mantissa registers 31, 32, and 41, 42, and the contentsin the exponent registers 33, 34, and 43, 44 individually, so that it isnot necessary to use a special converting circuit if the bit number ofthe mantissa portion in the floating decimal point data is longer thanthe bit length of the fixed decimal point data handled externally,thereby making it possible to process arithmetically and transfer on thebasis of a common clock signal (in this embodiment, 32 pulse signals persampling period). In the data transfer between processors 24 and 25,too, the floating decimal point data may be directly transferred in thesame format, and if the processor is divided into a plurality dependingon the content or quantity of the arithmetic processing, the sameprocessing precision as in a single processor is obtained.

As explained in detail herein, according to the invention, if the bitnumber of the mantissa in the floating decimal point data for arithmeticprocessing is longer than the bit length of the fixed decimal point datahandled externally, special converting circuitry is not needed, and itis possible to process arithmetically and transfer on a basis of acommon clock signal, and the precision does not deteriorate.

FIG. 48 is a block diagram showing a structure of a sound signalprocessor 21 in an embodiment of the invention. An analog sound signal,for example, from a radio receiver entered from an input terminal 22 isconverted into a digital signal in an analog/digital converter 23, andis supplied into a processor 24 realized by large scale integration orthe like. At the processor 24, the input digital sound signal isprocessed arithmetically or by delay for the purpose of tone control orthe like, and the output is sent into another processor 25. At thisprocessor 25, a different arithmetic processing is carried out, and athus processed digital sound signal is converted into an analog signalin a digital/analog converter 26, of which output is applied to a poweramplifier or the like connected to an output terminal 27.

In the thus composed sound signal processor 21, if the output led outinto the processor 24 from the analog/digital converter 23 and theoutput led out into the digital/analog converter 26 from the processor25 are stereo signals, supposing the right and left channels to have 16bits each, they are fixed decimal point data of 32 bits in total persampling period. By contrast, in the processors 24, 25, in order toenhance the dynamic range and S/N ratio, the sound signal is composed of16-bit mantissa portion and 4-bit exponent portion for each of the leftand right channels, so that the sound signal is handled as floatingdecimal point data of 40 bits in total per sampling period in arithmeticprocessing and data transfer.

The processor 24, in order to store the input data, comprises a 32-bitmantissa receiving register A11 composed of 16-bit left channel cellA11a and 16-bit right channel cell A11b, and an 8-bit exponent receivingregister A12 composed of 4-bit left channel cell A12a and 4-bit rightchannel cell A12b, in which the received data is given to a commoncontact 31 of a switch S11, and is selectively written into the mantissareceiving register A11 or exponent receiving register A12 respectivelyconnected to the individual contacts 32, 33. The processor 24 alsocomprises a 32-bit mantissa transmitting register B11 composed of 16-bitleft channel cell B11a and 16-bit right channel cell B11b, and an 8-bitexponent transmitting register B12 composed of 4-bit left channel cellB12a and 4-bit right channel cell B12b, in which the data from themantissa transmitting register B11 or exponent transmitting register B12is applied to the individual contacts 34, 35 of the switch S12, and isread out selectively from the common contact 36. The switching format ofthe switch S11 and switch S12 is controlled by a control circuit 38.

The processor 25 is composed the same as the processor 24, comprising amantissa receiving register A21 composed of 16-bit left channel cellA21a and 16-bit right channel cell A21b, exponent receiving register A22composed of 4-bit left channel cell A22a and 4-bit right channel cellA22b, mantissa transmitting register B21 composed of 16-bit left channelcell B21a and 16-bit right channel cell B21b, exponent transmittingregister B22 composed of 4-bit left cell B22a and 4-bit right cell B22b,switches S21, S22, and control circuit 39. The control circuits 38 and39 are coupled together by a line 40. The common contact 41 of theswitch S21 is connected to the common contact 36 of the switch S12through line 37, while one individual contact 42 is connected to themantissa receiving register A21 and the other individual contact 43 isconnected to the exponent receiving register A22. One individual contact44 of the switch S22 is connected to the mantissa transmitting registerB12 and the other individual contact 45 is connected to the exponenttransmitting register B22, while the common contact 46 is connected tothe digital/analog converter 26. In FIG. 48, numerals 16, 4 shown ineach register denote the number of bits in the store region of eachregister.

In this embodiment, at the processor 24 in the previous stage, thecommon contact 31 of the switch S11 keeps conduction with the individualcontact 32, while at the processor 25 in the later stage, the commoncontact 46 of the switch S22 keeps conduction with the individualcontact 44.

Therefore, the 32-bit fixed decimal point data from the analog/digitalconverter 23 is stored in the left and right channel cells A11a, A11b ofthe mantissa receiving register A11 of the processor 24, and isconverted into 4-bit floating decimal point data, and is stored in the4-bit register C11 composed of 20-bit left channel cell C11a and 20-bitright channel cell C11b. The data in the register C11 is arithmeticallyprocessed, and the data in the left channel cell C11a is stored in theleft channel cell B11a of the mantissa transmitting register B11 and theleft channel cell B12a of the exponent transmitting register B12, whilethe data in the right channel cell C11b of the register C11 is stored inthe right channel cell B11b of the mantissa transmitting register B11and right channel cell B12b of exponent transmitting register B12. Whilethe switch S12 is conducting with the individual contact 34, the switchS21 is conducting with the individual contact 42, and while the switchS12 is conducting with the individual contact 35, the switch S21 isconducting with the individual contact 43. In this way, since theswitching format of the switches S12, S21 is controlled in cooperation,the contents in the left and right channel cells B11a, B11b of themantissa transmitting register B11 are respectively transferred to theleft and right channel cells A21a, A21b of the mantissa receivingregister A21, while the contents in the left and right channel cellsB12a, B12b of the exponent transmitting register B12 are respectivelytransferred to the left and right channel cells A22a, A22b of theexponent receiving register A22.

In the processor 25, the left channel data received by the left channelcell A21a of the mantissa receiving register A21 and the left channelcell A22a of the exponent receiving register A22 is stored in the 20-bitleft channel cell C21a of the register C21; while the right channel datareceived by the right channel cell A21b of the mantissa receivingregister A21 and the right channel cell A22b of the exponent receivingregister A22 is stored in the 20-bit right channel cell C21b of theregister C21. Thus stored data are arithmetically processed, andconverted into 32-bit fixed decimal point data, and is applied from theleft and right channel cells B21a, B21b of the mantissa transmittingregister B21 into the digital/analog converter 26.

By controlling the switching format of the switches S11, S12, S21, andS22 in this manner, the processors 24, 25 can share a same integratedcircuit, and moreover this integrated circuit may be realized in arelatively simple circuit configuration, so that the cost for componentsmay be reduced.

According to the invention, hence, since the mantissa register andexponent register can be selectively connected to terminals fortransmission or terminals for reception, by the switching meanscontrolled in switching format by control means, if the formats of thedata transmitted are different, the circuit configuration can becommonly shared for transmission and reception, and therefore it isextremely advantageous for realizing the processor by integratedcircuits in particular.

What is claimed is:
 1. A data transfer apparatus for transferring serialdata to and from a controller, comprising:first memory means for storingat least one of command data and address data of the serial datatransferred from the controller, second memory means for storing a mainbody portion of the serial data transferred to and from the controller,and changeover means for selectively applying the serial datatransferred from the controller to either the first memory means or thesecond memory means, the second memory means including write/read meansfor selectively storing the main body portion of the serial datareceived from the controller and reading the main body portion of theserial data transmitted to the controller, the changeover meansincluding means for applying a clock signal received from the controllerto one of the first memory means or the second memory means inaccordance with a latch signal received from the controller.
 2. A datatransfer apparatus comprising a controller and a processor for mutuallytransferring serial data between the controller and theprocessor,wherein a signal line is disposed between the controller andthe processor for effecting a data write operation or data readoperation between the processor and controller in accordance with alevel of a signal delivered form the controller or processor, whereincounting means for counting a number of bits of transferred serial dataare provided in at least one of the controller and processor, whereinthe transferred serial data is made up of an address portion when a readoperation is effected and is made up of an address portion and a writedata portion when a write operation is effected, wherein said countingmeans includes a first counter means for counting the address portion ofthe transferred serial data and a second counter means for counting theaddress portion and the write data portion of the transferred serialdata, and wherein a corresponding write operation or read operation iscarried out upon counting of a specified number of bits of acorresponding one of said first and second counter means.
 3. A datatransfer system for mutually transferring serial data between acontroller and a processor,wherein a signal line is disposed between thecontroller and the processor for effecting a data write operation ordata read operation between the processor and controller in accordancewith a level of a signal delivered from the controller or processor,wherein the serial data as transferred is made up of an address portionand a write data portion and is devoid of a write command when a datawrite operation is effected, and wherein the serial data as transferredis made up of only an address portion and is devoid of a read commandwhen a data read operation is effected.